Backporting as an integrated strategy seems solid. That said the entire slide seems worrisome to me. This clinging to Moores law. 2 years cadence, like former soviet planning, only looks like shareholder communication. Its like if they just can inflate stock price enough, debt and the process challenges will go away. Reminds me a bit of the GF ppts when Mubadala took over. I simply cant take it serious.
Yeah, I'd take it a lot more seriously if it was on a 4- or 5-year cadence. That would give a lot more time to optimise and mature the process and eke out as much performance over time as possible.
This roadmap basically shows "we're done in 10 years" instead of "we have a solid framework for decades to come".
Intel CEO tries to change the culture inside. To educate they dont have to have 90% share everywhere. How is this fairytale roadmap going to help him? Sure you can change the naming and eg call 7++ for 5nm, but outside of that i cant see how this roadmap is possible.
Nothing says “You can trust us as a foundry partner” like a constant stream of misinformation about 10nm followed by doubling down on a nonsensical 10yr roadmap...
I agree with you, with the exponentially increasing costs for each new process node if anything I think new process nodes are going to slow down dramatically. I'll even be surprised if we ever even reach the 1.4nm they claim in their slide because that's only 7 silicon atoms wide.
Researchers have predicted for years a possible quantum death at around 5nm because quantum tunneling will be a serous issue in the trace lines at that size. And even if they can combat the tunneling each node smaller is basically halving the number of atoms in each trace and at some point they are going to reach a point where the costs just aren't worth it.
Projections are that the 5nm node is going to cost 20 billion for the equipment. I doubt there's more than two companies in the world that could even afford that. That cadence is just pure fantasy.
1.4nm is not the actual transistor pitch of that process target, anymore than the TSMC 7nm process transistor pitch is 7nm (it isn't).
These are just marketing names to simplify codification of fab process node generations - it makes it easier for the media and bloggers and such to refer to it without getting into the nitty gritty details.
They have already demonstrated that they are unable to keep the 2-year cadence in their 14nm to 10nm move which took them 6 years. If this is any indication they will not even be fully on 7nm by 2027. Well, I guess no harm in some marketing hype, to keep their current customers in the intel ecosystems now that AMD has a far better portfolio of products.
In the same event they have fully acknowledged the failure of 10nm, the reason being that they were trying to be too aggressive (aiming at a 2.7x improvement over 14nm), which caused all the trouble.
As a consequence, they dialed the 7nm goal into a more realistic 2.0x in comparison to 10nm, and with lessons learned from the 10nm debacle, they will hopefully manage. Before the 10nm problems, Intel was an absolute market leader in process technology, they just overstepped badly. With more realistic goals, they should get back on track.
Intel had announced that they were replacing their Tick Tock strategy (a new process node every 2 years) with a Process, Architecture, Optimization strategy (a new process node every 3 years). Essentially, Intel was saying that with the increasing complexity of developing a new node, the 3 years it took to get the 14nm process working would become the new normal. Now that Intel is again talking about introducing a new process node every two years, it becomes very relevant that Intel wasn't able to get either 14nm or 10nm done in a 2 year time frame.
Well, yes, this is a shareholder communication. If they can't attract shareholders, they won't have money to do the research. What would you do if you had to produce a single slide about the roadmap?
There's a difference between a little spin and promising jetpacks and moon colonies by 2029. I get that the CEO won't be around that long, but this is deeply frivolous and aimed at uneducated investors. And I'm not even outraged, because look at the times we're living in, but we should all be worried about the stock market when it's getting this stupid. Who the hell thinks tariffs are going away? Is it all just algorithms now and there's no BS metric yet?
Intel is first and foremost a semiconductor foundry. Their issues since 2015 remind me of the issues GlobalFoundaries had, which was a spin-off from the former AMD company. They just can't innovate and keep up with the competition when it comes to the lithography.
And their architecture, basically Skylake, also reminds me of AMD and their FX-series. For its time, the unified core was an advanced idea but it wasn't quite refined or efficient. The same can be said about the Core i7-9900K using a monolithic design, it's not refined or efficient enough to keep up with Ryzen (or Zen2).
The rational part wants me to see Intel innovate as soon as possible and rise back to the top for some healthy competition. Whereas there's a bigger part of me hoping this continues for a couple more years, to the point where mindshare of Intel is seen as "lower quality", with a much smaller marketshare, and massive drop in their company's cash reserves and stock prices. I want them to grovel. And I only want Intel to make a comeback when they've sorted out their chip fabrication and architecture, where they can out-compete AMD. I feel like if that long-term negative experience happens in the market, a lot of "bad blood" and "bloat" will be removed from their company... then maybe the industry will (learn something and) stay competitive for much longer: eg Remember the late 90's ??
I completely agree with you. I would like to see Intel keep getting sucker-punched for another year or two. They need to be humbled. If they are forced to shift their mindset from that of the market dominating goliath, to that of the underdog struggling to stay relevant, we will all benefit. Plus they deserve to be slapped around for a while, their market practices and complacency is catching up to them.
Sounds amazing, but I wouldnt call it optimistic like the article does. At this point it's just dishonest to promise this cadence. This news makes the rumor that sunny cove will be backported to 14nm more plausible.
Where did Intel PROMISE to hit this cadence on time? Posters here need to take a step back and allow people/companies have goals, even stretch goals. Intel may not hit their goals, but at least they should have them. Heck, it wasn't even Intel presenting this slide.
EUV will make 7 nm and 5 nm far easier than 14 nm and 10 nm. I personally doubt that 1.4 nm will be available in 2029. But still, don't condemn a company for striving and don't put words into their mouth pretending that research goals are a promise.
I think it's perfectly fair to call these projections dishonest. Word-lawyering over the word "promise" aside, they're very much signalling to the public (and shareholders) that they intend to deliver on a 2 year cadence. Given their behaviour throughout the 10nm debacle (it's fine... still fine... definitely fine... okay not fine yet but will be tomorrow... probably... 14nm is great by the way... etc.) we know we can't trust their roadmaps anymore, so why push such a tight cadence when we're all aware how unlikely it is?
That's right, thanks Spunjji. The word promise wasnt a good choice but I always find it very weird when people start saying others are wrong because the definitions of the words they used are not perfect, instead of focusing on the essence of the argument, and that is that the roadmap is dishonest, if it isn't a promise
Here’s what you are REALLY upset about: We are seeing the arrival of the Ceausescu moment, when the dictator rants his usual nonsense and everyone, instead of being vowed, bursts out laughing. You don’t want what is known by everyone to become common knowledge...
See the update to the article above. It wasn't even Intel stating 5 nm, 3 nm, 2 nm, and 1.4 nm. It was someone's alteration to Intel's slide. So, of course we should jump to the conclusion that it was Intel being dishonest?
When we commented we didn't know about that update. But seeing the original roadmap it's not really different. There's still a new node each 2 years. And the node names that they inserted are plausible, it's probably what they are gonna end up being called, or something similar. It's just names, it doesn't matter
This isn't a stretch goal, it's absolutely unrealistic. Intel know EUV is super expensive, and each generation is getting harder and more complicated to manufacture. Keep in mind even if the smallest traces are 7nm, the transistors are still locked at somewhere around 16-22nm (depends on the tech each fab uses). So as you go smaller you need new processes to raise a transistor with a wider gap out of the 7nm trace.
The costs of these shrinks is increasing dramatically. 16nm cost about $4billion, 14nm cost about $8billion, 10nm(7nm) cost upwards of $14Billion and 5nm is projecting costs of close to $20Billion just to build the fab. These costs are unsustainable with 2 year runs (you simply cannot recoup the fab build costs in that timeframe without increasing prices at the same rate), they'll need to push each node out to 6+ years going forward to be able to recoup the capital (build) costs while maintaining reasonable prices. Look at the Xeon-W workstation chips, it's two xeon chips stapled together and to cover their costs and margins the chip alone costs $7,000.
This part is ok actually. The fab doesn't fall apart after 2 years, and Intel has made moves into contract manufacturing. Without a modem business, we can wonder what they'll produce, but if they get that far, it should be easy enough to drum up business.
This is a situation where Intel will need to prove itself--at any time Intel could face years of delay, exactly as it has missed its guidance and roadmaps for several years as of now. The company has a lot of ground to recover--meanwhile it's pedal-to-the-metal at AMD--a moving target, certainly.
Talk is good and all, but until a product is in mass production and shows benefits of a new process node we are still pretty much where we were yesterday. I will be interested in seeing if Intel can deliver, but I have doubts to say the least given recent stumbles.
The sub 5nm R&D has to be extremely expensive. I'm almost certain costs will kill Moore's Law at some point before 2nm. All the fabs keep saying Moore's Law isn't dead but when it's that much more the so called "law" will die as fabs will want to milk each node to get R&D funding back out of it.
IIRC from my ASIC layout days, the advertised node number used to be the smallest drawn channel length in the minimum sized transistor. However, given that a transistor is more than just a gate, the size of a transistor is necessarily larger than the channel. It is also not square in dimensions and the ratio of length to width can vary (particularly when different gate types like finFET vs Gate All Around are used). So calculating the difference in number of transistors per given area is not as simple as the calculations put forth.
The level of consistency eroded a bit when the nodes label started corresponding to the smallest feature size (usually a DRAM cell feature) which up until recently loosely corresponded to about half the drawn channel length and varies between manufacturer.
Finally, the level of consistency was entirely lost when manufacturers started using node labels as marketing terms that no longer correspond to any particular feature size. Even within the same manufacturer on the same general node (lets say 7nm) the actual feature sizes can vary depending on which particular 7nm process you are using.
That all said, the nodes that have historically been targeted are generally targeted to produce roughly 2x the transistors in the same area. This doesn't always work out perfectly, particularly when the layout of the transistor changes to incorporate different gate types, but this is an example of letting Moore's Law drive the target.
So that was a fairly long winded way of saying I expect the 64x will be closer to the truth. That said, I believe that you are correct in your assertion that they should be using decimal places for nodes. This is likely marketing at work. Probably the reason they used 1.4nm was not any target feature size, but because it is 1/10 of 14nm and that looks good in marketing.
Since FinFet you are right the node names don't really mean much. Frankly they should be naming them by actually transistor densities but even then it can be bs.
Well 3nm's cost model is pretty much done if we are talking about TSMC. And it is not expensive from Apple, Huawei, Qualcomm perspective. Remember AWS, and now possibly Google and Microsoft are in the game as well. So Cost will not amortised with more players on board. High NA EUV should be required for 2nm, along with GAA that could double the price of 3nm again. ( For now it seems TSMC has decided 3nm wont be GAA, compared to Samsung rushing for GAA first )
Then there is 1.4nm. I believe it is here or Sub 1nm that we will see Moore's law being extended to 3 years instead of the current cadence.
Semember that TSMC 7nm is actyally 40-50nm... and same as Intel 10nm... The marketing nm Are getting really far out from reality in all manufacturers! What 1.4nm marketing means in reality? 30-40nm? Sure Intel, Samsung, and TSMC can go smaller, but in reality They Are now at 40-50nm... so the Atom level is not so near in reality.
Rather than complain about whose node name is or is not correct, remember that what matters is - TSMC is shipping products that achieve the promised 100MTR/mm^2 on 7nm - Intel is (barely) shipping products that achieve half their promised 100MTR/mm^2 on their 10nm
But your point about “operating at atom scale” is valid and needs to be said, repeatedly.
That's nonsense. N7 and P1274 are both using approx. 100 MTr/mm2 with their high density Libs, and Intel is shipping and products are already in the market (additionally to 10nm FPGAs). And these libs are only used for special use cases. For example AMDs Zen2-Chiplet only utilizes about 53 MTr/mm2 with their high perf design and it is therefore far away from the upper process limit, which should be no surprise, because AMD already has enough problems reaching high frequencies (which additionally is no surprise because of the shrinked node and smaller structures.)
but.. yet.. they are still very competive with intels high frequency cpus... point is ?? intels 10nm process.. isnt available on more then 4 cores.. and cant hit high frequencies..
At some point, I've been told that the price will reduce from CFETs and at <3nm, VFETs, meaning that things will go vertical. If you stand every gate on its end, it solves several problems at once. Imagine a wafer covered in little cFETs like a little forest. Each one might be 20-30nm long, because of the short channel effect, but they would only take up perhaps 9-15nm^2. That would be a 10x reduction on a 3x40nm finFET
7nm euv is much easier to do than 10nm without euv... you really seem to not know what this is really about. Intel 10nm will be the shortest nide Intel has ever made. Most likely we see longer time 7nm and 14nm and maybe even 22nm in Intel portfolio that we will see 10nm that will meet the end of line as soon as Intel 7nm euv is ready. Intel has so much money that They can develop their 14nm++++++, 10nm++ and 7nm and 5nm at the same time. They Are not depending on each others.
It’s not JUST EUV. Remember Intel claims that their 7nm will deliver 200MTr/mm^2 A stupid promise to make given that IceLake ships at half the promised 10nm density. But that’s the promise they made, and they will (justifiably!) be mocked when they drastically miss that, as I am user they will.
TSMC isn’t promising that sort of crazy upscaling for THEIR 5nm mass EUV...
So yeah it's been over 4 1/2 years since 14nm came out and 10nm desktop chips are still nowhere in sight and they suddenly expect to make node jumps every 2 years at even smaller sizes?
3nm in 2029 to me is a longshot let alone anything smaller.
The problems is not EUV, it is constant cluelessness. There was nothing stopping them running an EUV 10nm* line in parallel with the 10nm line. but at EVERY stage of the game they found an excuse not to do this. Hell they could backport EUV to 10nm right now if they wanted to (cf TSMC’s 7nm+) — but, like I said, constant cluelessness.
If they can do it, the plan looks good to me: lots of things make sense. However, can they really deliver a yearly improvement cadence and a 2-3 years development cycle, after what happened on 10nm? And also, will the ever-increasing costs justify the developments? How much will it cost to amortize the development for 2 and 1.4nm, on silicon? What would be the cost advantage of a foundry like TSMC, on such small/expensive node, over Intel's own fab?
TSMC is not better than Intel in foreseeing how a new PP will end. Do you know what happened to TSMC planar 20nm PP? How can you be sure it won't repeat?
You all think that because Intel has a halt with 10nm PP then everyone else is better than will never fail or have the same or similar issues in the future.
Unfortunately, new nodes are going to be so complex than anyone can fail or have big success with respect to the results of the competitors. As costs rise and new technical issues are encountered, materials and new technologies are the way to go. And none today knows who is going to do the best choices, now, tomorrow, next year and in next ones.
I don't think you got my point, or perhaps I did not explain myself clearly enough. Yes, issues on specific nodes can happen, but the smaller we go, the harder it will be for a private foundry to compete with a mammoth like TSMC (or Samsung, for that matters). TSMC is breaking ground for 3nm, and 5nm is sailing strong. Intel expects 20nm in 2020, 2 years after 7nm is in volume production.
The "mammoth" TSMC still has a revenue smaller than Intel. So Intel in not that small and is capable enough to keep their foundries up to date. Unless some problems occurs like those for 10nm. But if you think that is (ever) Intel managed to get their initial 10nm promises, TSMC would now be 4 years back.
Intel is creating its own 7nm (which are NOT TSMC 7nm) in parallel with 10nm PP. As said, TSMC can have all the plans they want like Intel has in this slide, but all that counts is HOW the PP is going to work. Their 20nm where quite advanced with respect to the other foundries, but it was just junk until they adopted FinFET as all the other foundries. At that time they were in par.
Like I said ... the roadmap looks good. If they can deliver it, they will be in good shape. If. Competition is good for everybody, so I certainly hope it will be the case, *but*, Intel is the last, or one of the last few companies with their own fab. No matter how big they are, it'll come a moment where it won't make sense, financially. I think we're there, or almost there, and I don't believe they can get to 1.4nm and stay competitive. That's my guess: time will tell.
" Intel is creating its own 7nm (which are NOT TSMC 7nm) in parallel with 10nm PP. " where did you read this from.. doesnt seem to be a mention of this in this article..
Huh? Don't you know Intel is already developing its 7nm PP right now? Or do you think they are going to wait for their 10nm problems to end before starting the development of the new PP? Just by curiosity, do you know how long it takes to develop a new PP?
dont you know how to post a source for your claims ? ie a link or mention of a website. its safe to assume that. but if all the companies that are able to make ICs get the equipment and tools to make them from the same handfull of companies, then for the most part.. the base design would be the same. if they would smart.. intel would be.. cause it could take them 3+ years before its ready.. and that being said.. this roadmap.. is bogus and garbage.. untill intel actually releases products for the given node. do you know how long it takes ???
look.. post links to your claims.. or your claims.. or just that ... yours.. nothing more
Well, considering 10nm issues I don't trust this plan at all. This backporting sounds ... troubling. Intel surely wishes they didn't have all those 10 nm problems or that at least that their CPUs could be remade to 14 nm process. But at the same time, backporting being an official strategy from now on means Intel doesn't trust their ability to offer great performance, yields or even basic ability to manufacture chips on their upcoming processes.
Backporting is the (very late) reply by intel to their current manufacturing problems. Any other company would hve back ported their new architecture to their current node once they realized their manufacturing problems. Not intel. They have been selling Skylake derivatives for 4+ years on 14nm process iterations. Their new architecture was entirely married with their process node and they have been waiting all this time for manufacturing to catch up. This backporting shows they are changing the way they design and implement new architecture to *NOT* fall back in that trap. Whether they will succeed is another matter...
Very aggressive road map. We'll see soon if 10nm was a single hiccup or a symptom of deeper problems. (by seeing when and how 7nm releases...)
To be fair, AMD was so far behind until recently there was no reason not to just keep refreshing. Even now, Skylake is still faster for high end gaming due to the clockspeed advantage. AMD is the better buy across most of the product stack, but Intel still has that.
Intel's not the better buy for high-end gaming - it's the better buy for *high refresh-rate 1080p gaming*. Anybody using VR / ultra-wide / 4K displays with high detail levels in recent games, which is what now constitutes high-end, is still going to be GPU limited.
Considering this is a conference on device(transistor) technology and a slide deck presented by a device(transistor) research and manufacturing partner, does backport here really mean what people here are hoping it means?
i.e. are they potentially talking about back porting transistor/wire layouts and optimizations (metal stacks, Via materials, etc) to slightly older process nodes
There is an element of that, a sort of cooperative DTCO between techniques to help improve older process node technologies. However as the graph shows, the new node is derived from the first gen of the previous node, so how much can be back-ported on the litho side is perhaps questionable.
They've definitely done things like this in the past. For example, 22FFL took the transistor fin from their 14nm, brought a modified version of a 14nm SRAM cell to 22FFL as the HCC SRAM, and those are just the things they publicly talked about. I'm sure there are other things they could bring over as well, like adaptations in the via/metal layers with new materials or modified double-damascene etc etc etc.
What I think everyone here is jumping to for 'backporting' is assuming this means Sunny Cove or Willow Cove etc being brought a process node. Nothing in any of these materials suggests that at all.
Roughly speaking (n) nano meters is still the same no matter what technology is used to make it (i.e. same transistor count per area, hence the same power use). It will mean better yields, which in turn means lower supply of low end chips (i3, pentium, celeron) and some low volume weirdos. Improving architecture and design is a different matter, which until now was not called backporting but it is now.
The backport opportunity just shows a underline problems of the future PPs: costs. Complexity and design costs will just have an great impact on the choice of the PP to chose, and seeing that since 22nm transistor/cost curve has turned negative, it is even possible that for the next PPs, when you are not forced to use the latest shiny expensive new PP for performance/consumption issues, you may get cheaper designs using older PP.
MCM designs will also help in reducing the needs of smaller transistors at all costs.
It's a bit of a stretch to claim that they're "already on" 10nm, considering they've only managed to actually ship a handful of mobile parts on that process node. Intel has been stuck on 14nm for nearly six years and is *still* struggling to manage decent enough yields on 10nm to actually sell them. Are we really to believe that they're capable of a node shrink every other year - especially when each further shrink is going to be harder than the last?
This is just intel trying to salvage some industry faith after getting hammered by AMD for the last couple years.
10nm was broken, but 7nm is an entirely different process using EUV. As long as they kept development of it active, the 10nm problems should not really impact it.
7nm EUV is realistically easier to do then the 10nm process, since EUV solves many of the problems that a small DUV process had to overcome.
EUV is not exactly the holy grail of photolithography. It solves plenty of DUV's problems (largely because the much tighter wavelength can let fabs etch patterns in just one step instead of 2 to 4 steps) but it has its own set of problems : high LER (Line Edge Rougness) of features, the step & scan machines have much lower energy efficiency (resulting in quite higher energy bills) due to much higher losses of EUV light from the source to the target, the optics need to be orders of magnitude more precise and are thus (also) far more expensive, and more or less the same applies to the masks and their pellicles, both of which need to be highly reflective (at least 85 - 90%).
In short EUV is a much more delicate, elaborate, and *far* more expensive business than DUV, which my guess is what forced GloFo to bow down from the EUV game. Intel, TSMC and Samsung have the monies to invest in EUV R&D and build EUV fabs with many ASML's EUV scanners, but I strongly doubt anyone else can do it. As for manufacturers of EUV scanners ASML will almost certainly remain the only company in the world in the future as well. Their monopoly naturally allows them to charge whatever they think the trio of companies above can afford to pay, nothing less and nothing more.
AFAIK, EUV is more expensive for each mask, but it requires less masks than DUV. That's why TSMC 7nm+ PP is looked for lowering production costs and raise the yields, as all those multiple patterning processes will no be needed anymore.
Probably he big drawbacks of EUV is that is is slower to produce. So it needs more scanner, or faster more expensive ones. And that's also why EUV is not applied to all layers in its first version, but only on the critical ones that on multipatterning raise DUV costs and lower yields..
Considering Intel's roadmap. Has Intel released 10nm silicon in the desktop, workstation or server space yet? AFAIK, the answer is a resounding NO!
When/if Intel does 10nm in those spaces (say 2020) will they be at lower GHz then the latest 14nm silicon due to heat issues (e. g. by not adopting a chiplet strategy and going with a monolithic single chip strategy in the face of heat issues)?
I seriously doubt yield issues at 10nm, simply because Intel has had five (going on six) years to solve that issue.
I guess what I'm trying to say is that Intel did not learn from their own previous history of chasing GHz. That Intel has pushed GHz at the 14nm node at the expense of the 10nm node. In other words, if 10mn is slower than 14nm who would buy 10nm? Assuming that core counts (needs to go up), power (needs to go down) and pricing (needs to go down) don't change significantly.
It will be like six years for 10nm desktop silicon. What's up with that?
1. Those date ( year ) are all Q4, and volume isn't in the quantity we traditionally expects, so unless they could push 7nm faster, it may be better to shift expectation or general conciseness of year by 1. Effectively 7nm is 2022, and 1.4nm is 2030.
2. I was surprised the article has no mention of Jim Keller, this method of delivery and back porting or design and node detachment is called train delivery in Apple or AMD. Something he mentioned in the Anandtech interview.
3. The three stage manufacturing method is also basically the same as TSMC, N7, N7P / + and N6, with three iteration of each node. ( EUV being exception )
4. If Intel has fixated its 5nm on High NA EUV they will be repeating the same 10nm mistake again. Not only do I doubt ASML will have those machine on time, delivery of it will also be extremely limited. If I remember correctly ASML only delivered single digit of their EUV during first year, ~20 during 2nd. And in case Samsung is not trying to grab everyone of them, HVM on first year of introduction sounds like a very risky move.
5. Still wish some industry perspective on economical model, although the recent Semienginnering revision of 3nm cost down to Sub $2B seems like a big improvement, it is still the elephant in the room.
Why would anyone believe a word Intel says about anything now? They have LIED for years about 10nm - how many times have we heard that 10nm is now “shipping”. They have LIED for years regarding security and shipped countless processors with serious vulnerabilities that they knew about. And now AGAIN they are LYING about benchmarks. Such a deceitful and dishonest company.
Plenty of people on here alluding to the same thing i said. Intel are an untrustworthy company with a long history of lies and deceit. Deal with it fanboy.
lol, back-porting as part of strategy, they are preparing for more 10nm like delays, interesting learning let they introduce back-tick, back-tock philosophy
The problem is as of today, Intel is having their biggest competitor rising in an incredible fashion... not AMD... TSMC. I am betting on TSMC to keep the lead.
Neither. TSMC dropped the ball on 32nm (cancelled the node late, leaving both GPU and mobile chip partners high and dry) and fumbled it on 20nm (power characteristics were so bad that they probably should have cancelled it; again, GPU partners notably skipped that one).
Intel have historically been better, but 14nm was a mess and 10nm is an absolute travesty. I'm not sure it makes sense to assume they'll continue in the same vein, but obviously we can't just rely on their statements to the contrary after 4+ years of "10nm tomorrow".
In summary, the solid bet is that they'll both make a few questionable decisions that will hold up their process technology have wider impacts on the industry. Anything more specific than that is speculation.
This. People easily forget history for their convenience or due to ignorance. We are now in a situation where Intel has failed a PP step, while TSMC was successful but did not make great things either. They just anticipated everyone that decided to use 7nm with EUV. We will see how things will be when Samsung and Intel will come out with their EUV PPs. That's the joint point where to do comparisons and see who will suffer.
" People easily forget history for their convenience or due to ignorance." yes they do. like the shady dealings, theats and bribes intel made to shut amd out of the market, or the constant lies about 10nm being on track, the criticism AMD got for its power usage before Zen with their chips, but now that intel is using more power for theirs, it seems to be ok... etc etc etc
This seems like a shrewd plan, they’re hedging with this parallel feature size plan. Basically they can choose to release a new CPU on either a new node or the ++ size, depending on what is developed enough to work.
In 10 years 2029, Intel will file for chapter 11 .... they will be in 10++++ for a long long time, that is what intel does best, to fine tune a process. If AMD/TSMC is talking about anything beyond 3nm, I will sell all my AMD shares. I do not believe in anything smaller than 3nm yield will be in big big trouble.
There's a bizarre thing on enthusiast web sites where many people seem to think desktops are the only important market segment for PC CPUs instead of the least reality where the only way you can argue they aren't the least important market segment is because of halo effects.
It isn't bizarre at all. Those websites are correct. If you aren't selling desktop, hedt, and server processors on the same node as your competitors, it's because you failed in R&D and you can't produce them at all. You might be the last person on Earth who didn't know that AMD is having the biggest year in it's history, and it's not because of irrelevant laptop chips. Try reading a newspaper.
They also sold cannon lake products back in the day, though it was also mostly DOA. And there is no H Series Ice Lake for mobile workstations. Pretty limited product stack from my perspective.
Let's do a naive and rough calculation of the projected transistor density of Intel's 1.4nm node. Intel's 10nm node has 100 million transistors per mm^2 (MTr/mm^2), which provides a nice round base for the calculation. Assuming Intel retains a doubling on average of transistors with each of their number nodes, their 7nm node will 200 MTr/mm^2, their 5nm node will have 400 MTr/mm^2 ... and finally their 1.4nm node will have 3.2 *billion* transistors per mm^2.
That is almost certainly physically impossible, so Intel might rather add +80% more transistors on average with each number node. That still means ~1.9 billion transistors per mm^2 at 1.4nm. A +70% extra transistors on average means ~1.4 billion transistors at 1.4nm. I have no idea if that is feasible, but Intel will probably be even less aggressive, maybe by adding +60% extra transistors on average until 2029 (or, much more likely, 2035), which would result in ~1 billion transistors per mm^2 at 1.4nm.
Even so, that would be the end of the road for transistors, unless new materials provide a speedup at lower densities.
p.s. My calculation employs as a base Intel's high performance 10nm node, which has the highest transistor density. That's the node with the ~100 MTr/mm^2. Intel has two other 10nm nodes though, one for moderate performance (moderate density) and one for lower performance/density. I cannot recall precise numbers but I think the moderate performance 10nm node (which, to my knowledge, is what Ice Lake-U/Y SoCs are fabbed on) has a density around 80 MTr/mm^2 and the lower density 10nm node has 55 to 60 MTr/mm^2. I did not take into account these other two nodes because the calculation would become quite more complex. Intel's high density 10nm node is intended for -H & -S desktop CPUs (which do not exist and apparently will not exist in the entire 2020 either, due to poor yields) and Xeon CPUs.
I am surprised they never thought to try for 12nm although at this stage it probably is almost identical to 14+++. I wonder if TSMC and Samsung are using ASML or are they with some one else for equipment. I REMEMBER the Intel are shareholders of ASML and have burnt bridges so can not go with some one else. Maybe the issue is with the 1st Batch of ASML equipment and Intel do not want to retool.
Noone has really done a "12nm" node, its just another name. What Intel calls 14+++, you can get from eg. TSMC as a 12nm process - a refined 14nm process.
So hang on, let me get this straight. Intel is stuck on 14nm for the desktop, with 10nm mobile chips trickling through the pipeline. Yet now, somehow, after being stuck on 14nm for 4 years, Intel will squeeze in 5 MORE node shifts after 10nm in the next 9 years!?
The slide is meaningless. It's a pie-in-the-sky presentation, not anything based on engineering work that is actually in-progress. That should be obvious given how many years it projects ahead.
I am rooting for Intel for the sake of competition in the space, better products at better prices for the consumer and generally moving technology forward. The resurgence of AMD is in my mind the best thing that has happened in this space in a very long time. If Intel can get their company in order and make a comeback with competitive products, that would be a new golden era. That said, this looks overly optimistic from Intels side. I'd be very surprised if they can execute on that cadence. Their history does not speak for them either.
rooting for intel for the sake of competition ?? considering they stagnated the cpu market for 3 or 4 years... no thanks... better to root for amd... at least they are doing something to move the cpu market forward.. more so then intel has
The presentation in the slide of the future should at least better be called: In more we trust. That is of course meant for the interested parties, who have lost trust. For Intel to get it back, the slide will be contra-productive. Building on an old prophecy and no longer valid law(s) is not the way to do it. Better is to express a new mission and goals and then a strategy to obtain these. The setup should be built on frontier-science, technical possibilities, ecological and economical aspects as well as political considerations. It is doubtful that anyone these days can give a reasonably reliable outlook for the node in 2029. It’s is furthermore questionable if the node is the most trust-giving characteristic of the forthcoming products.
ASML The slide of ASML gives even more ashtonishment. Is it the mother of all slides or a child? If a derivate, are there no other clients of ASML with other slides? Commercially not a good move.
BACK TO THE FUTURE If the slide is a kind of attempt to influence the future. Expect some new ones in this theatre soon.
What I REALLY want to see is a 5 year roadmap of Intel's chipsets. CPUs are nice and all, but the real meat is what they run on. Hopefully the good Dr. can make this a priority, right after he looks at my knee...:-)
Personally I wouldn't mind seeing ice lake running @ 5ghz on 14nm with it's 18% IPC gain. Maybe that's not good for the future of cpu short term but would be the fastest chip around in a long time.
At some point all chip manufacturers will have to take a long look at IPC as they will no longer be able to brute Force advancements out of process nodes.
Feels a lot like the netburst days all over again. The mobile cores are running lower clocks at lower speeds less power consumption with most of the performance still there.
Anyone remember when the adapters to convert laptop chips to desktop motherboards were around? Led benches for over a year before Intel launched the core models.
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quantumshadow44 - Tuesday, December 10, 2019 - link
sounds good.krumme - Tuesday, December 10, 2019 - link
Backporting as an integrated strategy seems solid.That said the entire slide seems worrisome to me. This clinging to Moores law. 2 years cadence, like former soviet planning, only looks like shareholder communication. Its like if they just can inflate stock price enough, debt and the process challenges will go away. Reminds me a bit of the GF ppts when Mubadala took over. I simply cant take it serious.
phoenix_rizzen - Tuesday, December 10, 2019 - link
Yeah, I'd take it a lot more seriously if it was on a 4- or 5-year cadence. That would give a lot more time to optimise and mature the process and eke out as much performance over time as possible.This roadmap basically shows "we're done in 10 years" instead of "we have a solid framework for decades to come".
krumme - Wednesday, December 11, 2019 - link
Intel CEO tries to change the culture inside. To educate they dont have to have 90% share everywhere. How is this fairytale roadmap going to help him? Sure you can change the naming and eg call 7++ for 5nm, but outside of that i cant see how this roadmap is possible.fizzypop - Wednesday, December 11, 2019 - link
This is basically saying we are going to lose market share but might get lucky as we try to diversify.name99 - Wednesday, December 11, 2019 - link
Nothing says “You can trust us as a foundry partner” like a constant stream of misinformation about 10nm followed by doubling down on a nonsensical 10yr roadmap...rahvin - Wednesday, December 11, 2019 - link
I agree with you, with the exponentially increasing costs for each new process node if anything I think new process nodes are going to slow down dramatically. I'll even be surprised if we ever even reach the 1.4nm they claim in their slide because that's only 7 silicon atoms wide.Researchers have predicted for years a possible quantum death at around 5nm because quantum tunneling will be a serous issue in the trace lines at that size. And even if they can combat the tunneling each node smaller is basically halving the number of atoms in each trace and at some point they are going to reach a point where the costs just aren't worth it.
Projections are that the 5nm node is going to cost 20 billion for the equipment. I doubt there's more than two companies in the world that could even afford that. That cadence is just pure fantasy.
soresu - Sunday, December 15, 2019 - link
Ugh, how many times must it be said?1.4nm is not the actual transistor pitch of that process target, anymore than the TSMC 7nm process transistor pitch is 7nm (it isn't).
These are just marketing names to simplify codification of fab process node generations - it makes it easier for the media and bloggers and such to refer to it without getting into the nitty gritty details.
Spunjji - Wednesday, December 11, 2019 - link
100% agreed.sharath.naik - Wednesday, December 11, 2019 - link
They have already demonstrated that they are unable to keep the 2-year cadence in their 14nm to 10nm move which took them 6 years. If this is any indication they will not even be fully on 7nm by 2027. Well, I guess no harm in some marketing hype, to keep their current customers in the intel ecosystems now that AMD has a far better portfolio of products.nevcairiel - Wednesday, December 11, 2019 - link
In the same event they have fully acknowledged the failure of 10nm, the reason being that they were trying to be too aggressive (aiming at a 2.7x improvement over 14nm), which caused all the trouble.As a consequence, they dialed the 7nm goal into a more realistic 2.0x in comparison to 10nm, and with lessons learned from the 10nm debacle, they will hopefully manage. Before the 10nm problems, Intel was an absolute market leader in process technology, they just overstepped badly. With more realistic goals, they should get back on track.
KAlmquist - Monday, December 16, 2019 - link
Intel had announced that they were replacing their Tick Tock strategy (a new process node every 2 years) with a Process, Architecture, Optimization strategy (a new process node every 3 years). Essentially, Intel was saying that with the increasing complexity of developing a new node, the 3 years it took to get the 14nm process working would become the new normal. Now that Intel is again talking about introducing a new process node every two years, it becomes very relevant that Intel wasn't able to get either 14nm or 10nm done in a 2 year time frame.p1esk - Thursday, December 12, 2019 - link
Well, yes, this is a shareholder communication. If they can't attract shareholders, they won't have money to do the research. What would you do if you had to produce a single slide about the roadmap?nico_mach - Thursday, December 12, 2019 - link
There's a difference between a little spin and promising jetpacks and moon colonies by 2029. I get that the CEO won't be around that long, but this is deeply frivolous and aimed at uneducated investors. And I'm not even outraged, because look at the times we're living in, but we should all be worried about the stock market when it's getting this stupid. Who the hell thinks tariffs are going away? Is it all just algorithms now and there's no BS metric yet?milkywayer - Tuesday, December 10, 2019 - link
Only on the slides if we look at their track record. I've a feeling we'll be on 10nm++++++++ in 2029. Sorry if I missed a + there.qlum - Tuesday, December 10, 2019 - link
Nah, they will just be reintroducing 65nm to cope with supply shortages.Kangal - Wednesday, December 11, 2019 - link
Intel is first and foremost a semiconductor foundry.Their issues since 2015 remind me of the issues GlobalFoundaries had, which was a spin-off from the former AMD company. They just can't innovate and keep up with the competition when it comes to the lithography.
And their architecture, basically Skylake, also reminds me of AMD and their FX-series. For its time, the unified core was an advanced idea but it wasn't quite refined or efficient. The same can be said about the Core i7-9900K using a monolithic design, it's not refined or efficient enough to keep up with Ryzen (or Zen2).
The rational part wants me to see Intel innovate as soon as possible and rise back to the top for some healthy competition. Whereas there's a bigger part of me hoping this continues for a couple more years, to the point where mindshare of Intel is seen as "lower quality", with a much smaller marketshare, and massive drop in their company's cash reserves and stock prices. I want them to grovel. And I only want Intel to make a comeback when they've sorted out their chip fabrication and architecture, where they can out-compete AMD. I feel like if that long-term negative experience happens in the market, a lot of "bad blood" and "bloat" will be removed from their company... then maybe the industry will (learn something and) stay competitive for much longer: eg Remember the late 90's ??
jkh - Thursday, December 12, 2019 - link
I completely agree with you. I would like to see Intel keep getting sucker-punched for another year or two. They need to be humbled. If they are forced to shift their mindset from that of the market dominating goliath, to that of the underdog struggling to stay relevant, we will all benefit. Plus they deserve to be slapped around for a while, their market practices and complacency is catching up to them.Adonisds - Tuesday, December 10, 2019 - link
Sounds amazing, but I wouldnt call it optimistic like the article does. At this point it's just dishonest to promise this cadence.This news makes the rumor that sunny cove will be backported to 14nm more plausible.
dullard - Tuesday, December 10, 2019 - link
Where did Intel PROMISE to hit this cadence on time? Posters here need to take a step back and allow people/companies have goals, even stretch goals. Intel may not hit their goals, but at least they should have them. Heck, it wasn't even Intel presenting this slide.EUV will make 7 nm and 5 nm far easier than 14 nm and 10 nm. I personally doubt that 1.4 nm will be available in 2029. But still, don't condemn a company for striving and don't put words into their mouth pretending that research goals are a promise.
Spunjji - Wednesday, December 11, 2019 - link
I think it's perfectly fair to call these projections dishonest. Word-lawyering over the word "promise" aside, they're very much signalling to the public (and shareholders) that they intend to deliver on a 2 year cadence. Given their behaviour throughout the 10nm debacle (it's fine... still fine... definitely fine... okay not fine yet but will be tomorrow... probably... 14nm is great by the way... etc.) we know we can't trust their roadmaps anymore, so why push such a tight cadence when we're all aware how unlikely it is?It doesn't smell right.
Adonisds - Wednesday, December 11, 2019 - link
That's right, thanks Spunjji. The word promise wasnt a good choice but I always find it very weird when people start saying others are wrong because the definitions of the words they used are not perfect, instead of focusing on the essence of the argument, and that is that the roadmap is dishonest, if it isn't a promisename99 - Wednesday, December 11, 2019 - link
Here’s what you are REALLY upset about:We are seeing the arrival of the Ceausescu moment, when the dictator rants his usual nonsense and everyone, instead of being vowed, bursts out laughing.
You don’t want what is known by everyone to become common knowledge...
dullard - Thursday, December 12, 2019 - link
See the update to the article above. It wasn't even Intel stating 5 nm, 3 nm, 2 nm, and 1.4 nm. It was someone's alteration to Intel's slide. So, of course we should jump to the conclusion that it was Intel being dishonest?Adonisds - Friday, December 13, 2019 - link
When we commented we didn't know about that update. But seeing the original roadmap it's not really different. There's still a new node each 2 years. And the node names that they inserted are plausible, it's probably what they are gonna end up being called, or something similar. It's just names, it doesn't matterrahvin - Wednesday, December 11, 2019 - link
This isn't a stretch goal, it's absolutely unrealistic. Intel know EUV is super expensive, and each generation is getting harder and more complicated to manufacture. Keep in mind even if the smallest traces are 7nm, the transistors are still locked at somewhere around 16-22nm (depends on the tech each fab uses). So as you go smaller you need new processes to raise a transistor with a wider gap out of the 7nm trace.The costs of these shrinks is increasing dramatically. 16nm cost about $4billion, 14nm cost about $8billion, 10nm(7nm) cost upwards of $14Billion and 5nm is projecting costs of close to $20Billion just to build the fab. These costs are unsustainable with 2 year runs (you simply cannot recoup the fab build costs in that timeframe without increasing prices at the same rate), they'll need to push each node out to 6+ years going forward to be able to recoup the capital (build) costs while maintaining reasonable prices. Look at the Xeon-W workstation chips, it's two xeon chips stapled together and to cover their costs and margins the chip alone costs $7,000.
extide - Wednesday, December 11, 2019 - link
There are no dual die Xeon W products, FYI. You are thinking of Cascade Lake AP ... and they cost a LOT more than $7k .. closer to $50k.nico_mach - Thursday, December 12, 2019 - link
This part is ok actually. The fab doesn't fall apart after 2 years, and Intel has made moves into contract manufacturing. Without a modem business, we can wonder what they'll produce, but if they get that far, it should be easy enough to drum up business.And anyway, it's not going to be every two years.
versesuvius - Wednesday, December 11, 2019 - link
Just good? It is awsome. As of this moment I am the greatest man alive back ported to me!!!Opencg - Wednesday, December 11, 2019 - link
I just look up to myself and then I raise myself up and I just get cooler all the time.WaltC - Saturday, December 21, 2019 - link
This is a situation where Intel will need to prove itself--at any time Intel could face years of delay, exactly as it has missed its guidance and roadmaps for several years as of now. The company has a lot of ground to recover--meanwhile it's pedal-to-the-metal at AMD--a moving target, certainly.PeachNCream - Tuesday, December 10, 2019 - link
Talk is good and all, but until a product is in mass production and shows benefits of a new process node we are still pretty much where we were yesterday. I will be interested in seeing if Intel can deliver, but I have doubts to say the least given recent stumbles.goatfajitas - Tuesday, December 10, 2019 - link
Exactly. Not released in "small quantities" like the current 10nm but in mass production. Until then it doesn't mean anything.cosmotic - Tuesday, December 10, 2019 - link
If by yesterday you mean 2015 which is when intel started shipping 14nm product which is still the only product being shipped in bulk.FreckledTrout - Tuesday, December 10, 2019 - link
The sub 5nm R&D has to be extremely expensive. I'm almost certain costs will kill Moore's Law at some point before 2nm. All the fabs keep saying Moore's Law isn't dead but when it's that much more the so called "law" will die as fabs will want to milk each node to get R&D funding back out of it.edzieba - Tuesday, December 10, 2019 - link
If you couch Moore's Law in respect to cost/transistor, it died when the 1.5nm gate oxide limit was hit and cost/transistor inflected at 22nm.peevee - Tuesday, December 10, 2019 - link
It is dead, they just keep reducing the numbers of fake nanometers (long meaningless by this point).nandnandnand - Tuesday, December 10, 2019 - link
Keeping the mind that the names don't mean anything, shouldn't a 1.4nm node have 100 times the transistor density of the 14nm node?ishould - Tuesday, December 10, 2019 - link
No density doesn't work like that. Assuming ideal scaling of 2x every node, it should have 14-10-7-5-3-2-1.4 = 2^6 = 64x density. In theory.nandnandnand - Tuesday, December 10, 2019 - link
14^2 / 10^2 = 1.96 and so on.Going from 14nm down to 1.4nm you get: 1.96 * 2.04 * 1.96 * 2.78 * 2.25 * 2.04 = 100x
The derailment happens from 5nm to 3nm. 25/9 = 2.777778
If they want to maintain the fiction, they should call the nodes 3.5nm, 2.5nm, and 1.75nm. Going from 14nm to 1.75nm = exactly 64x.
Somehow, I don't think the 100x is a mistake. Although the real world increase won't exactly match the increase predicted by marketing node names.
BurntMyBacon - Wednesday, December 11, 2019 - link
IIRC from my ASIC layout days, the advertised node number used to be the smallest drawn channel length in the minimum sized transistor. However, given that a transistor is more than just a gate, the size of a transistor is necessarily larger than the channel. It is also not square in dimensions and the ratio of length to width can vary (particularly when different gate types like finFET vs Gate All Around are used). So calculating the difference in number of transistors per given area is not as simple as the calculations put forth.The level of consistency eroded a bit when the nodes label started corresponding to the smallest feature size (usually a DRAM cell feature) which up until recently loosely corresponded to about half the drawn channel length and varies between manufacturer.
Finally, the level of consistency was entirely lost when manufacturers started using node labels as marketing terms that no longer correspond to any particular feature size. Even within the same manufacturer on the same general node (lets say 7nm) the actual feature sizes can vary depending on which particular 7nm process you are using.
That all said, the nodes that have historically been targeted are generally targeted to produce roughly 2x the transistors in the same area. This doesn't always work out perfectly, particularly when the layout of the transistor changes to incorporate different gate types, but this is an example of letting Moore's Law drive the target.
So that was a fairly long winded way of saying I expect the 64x will be closer to the truth. That said, I believe that you are correct in your assertion that they should be using decimal places for nodes. This is likely marketing at work. Probably the reason they used 1.4nm was not any target feature size, but because it is 1/10 of 14nm and that looks good in marketing.
FreckledTrout - Wednesday, December 11, 2019 - link
Since FinFet you are right the node names don't really mean much. Frankly they should be naming them by actually transistor densities but even then it can be bs.Adonisds - Wednesday, December 11, 2019 - link
Since 14nm to 10nm is 2.7 scaling, a better projection would be 86x densityCiccioB - Thursday, December 12, 2019 - link
No.There's not a 10->14nm with 2.7x density gain.
Intel tried, but failed.
ksec - Tuesday, December 10, 2019 - link
Well 3nm's cost model is pretty much done if we are talking about TSMC. And it is not expensive from Apple, Huawei, Qualcomm perspective. Remember AWS, and now possibly Google and Microsoft are in the game as well. So Cost will not amortised with more players on board. High NA EUV should be required for 2nm, along with GAA that could double the price of 3nm again. ( For now it seems TSMC has decided 3nm wont be GAA, compared to Samsung rushing for GAA first )Then there is 1.4nm. I believe it is here or Sub 1nm that we will see Moore's law being extended to 3 years instead of the current cadence.
haukionkannel - Wednesday, December 11, 2019 - link
Semember that TSMC 7nm is actyally 40-50nm... and same as Intel 10nm... The marketing nm Are getting really far out from reality in all manufacturers! What 1.4nm marketing means in reality? 30-40nm?Sure Intel, Samsung, and TSMC can go smaller, but in reality They Are now at 40-50nm... so the Atom level is not so near in reality.
name99 - Wednesday, December 11, 2019 - link
Rather than complain about whose node name is or is not correct, remember that what matters is- TSMC is shipping products that achieve the promised 100MTR/mm^2 on 7nm
- Intel is (barely) shipping products that achieve half their promised 100MTR/mm^2 on their 10nm
But your point about “operating at atom scale” is valid and needs to be said, repeatedly.
back2future - Friday, December 13, 2019 - link
Wouldn't it be more useful then defining transistor density on comparable volume?https://arstechnica.com/information-technology/201...
https://cdn.arstechnica.net/wp-content/uploads/201...
AnGe85 - Thursday, December 19, 2019 - link
That's nonsense. N7 and P1274 are both using approx. 100 MTr/mm2 with their high density Libs, and Intel is shipping and products are already in the market (additionally to 10nm FPGAs).And these libs are only used for special use cases. For example AMDs Zen2-Chiplet only utilizes about 53 MTr/mm2 with their high perf design and it is therefore far away from the upper process limit, which should be no surprise, because AMD already has enough problems reaching high frequencies (which additionally is no surprise because of the shrinked node and smaller structures.)
Korguz - Friday, December 20, 2019 - link
but.. yet.. they are still very competive with intels high frequency cpus... point is ??intels 10nm process.. isnt available on more then 4 cores.. and cant hit high frequencies..
fabmonkey - Thursday, December 12, 2019 - link
At some point, I've been told that the price will reduce from CFETs and at <3nm, VFETs, meaning that things will go vertical. If you stand every gate on its end, it solves several problems at once. Imagine a wafer covered in little cFETs like a little forest. Each one might be 20-30nm long, because of the short channel effect, but they would only take up perhaps 9-15nm^2. That would be a 10x reduction on a 3x40nm finFETschizoide - Tuesday, December 10, 2019 - link
I'll wager 1000 quatloos that 2023 has Intel on the 10nm+++++++ process with 7nm nowhere to be found.peevee - Tuesday, December 10, 2019 - link
Names are cheap to give.haukionkannel - Wednesday, December 11, 2019 - link
7nm euv is much easier to do than 10nm without euv... you really seem to not know what this is really about. Intel 10nm will be the shortest nide Intel has ever made.Most likely we see longer time 7nm and 14nm and maybe even 22nm in Intel portfolio that we will see 10nm that will meet the end of line as soon as Intel 7nm euv is ready. Intel has so much money that They can develop their 14nm++++++, 10nm++ and 7nm and 5nm at the same time. They Are not depending on each others.
name99 - Wednesday, December 11, 2019 - link
It’s not JUST EUV. Remember Intel claims that their 7nm will deliver 200MTr/mm^2A stupid promise to make given that IceLake ships at half the promised 10nm density. But that’s the promise they made, and they will (justifiably!) be mocked when they drastically miss that, as I am user they will.
TSMC isn’t promising that sort of crazy upscaling for THEIR 5nm mass EUV...
Ushio01 - Tuesday, December 10, 2019 - link
So yeah it's been over 4 1/2 years since 14nm came out and 10nm desktop chips are still nowhere in sight and they suddenly expect to make node jumps every 2 years at even smaller sizes?3nm in 2029 to me is a longshot let alone anything smaller.
nandnandnand - Tuesday, December 10, 2019 - link
Maybe lack of EUV is what screwed them. Things could speed up once they start using it.ishould - Tuesday, December 10, 2019 - link
I've heard they had a hell of a time with quad-patterning on 10nm. That and trying to get a 2.7x density increase instead of a "normal" 2xname99 - Wednesday, December 11, 2019 - link
The problems is not EUV, it is constant cluelessness.There was nothing stopping them running an EUV 10nm* line in parallel with the 10nm line. but at EVERY stage of the game they found an excuse not to do this.
Hell they could backport EUV to 10nm right now if they wanted to (cf TSMC’s 7nm+) — but, like I said, constant cluelessness.
yankeeDDL - Tuesday, December 10, 2019 - link
If they can do it, the plan looks good to me: lots of things make sense.However, can they really deliver a yearly improvement cadence and a 2-3 years development cycle, after what happened on 10nm?
And also, will the ever-increasing costs justify the developments? How much will it cost to amortize the development for 2 and 1.4nm, on silicon? What would be the cost advantage of a foundry like TSMC, on such small/expensive node, over Intel's own fab?
CiccioB - Tuesday, December 10, 2019 - link
TSMC is not better than Intel in foreseeing how a new PP will end.Do you know what happened to TSMC planar 20nm PP?
How can you be sure it won't repeat?
You all think that because Intel has a halt with 10nm PP then everyone else is better than will never fail or have the same or similar issues in the future.
Unfortunately, new nodes are going to be so complex than anyone can fail or have big success with respect to the results of the competitors.
As costs rise and new technical issues are encountered, materials and new technologies are the way to go. And none today knows who is going to do the best choices, now, tomorrow, next year and in next ones.
yankeeDDL - Wednesday, December 11, 2019 - link
I don't think you got my point, or perhaps I did not explain myself clearly enough.Yes, issues on specific nodes can happen, but the smaller we go, the harder it will be for a private foundry to compete with a mammoth like TSMC (or Samsung, for that matters). TSMC is breaking ground for 3nm, and 5nm is sailing strong. Intel expects 20nm in 2020, 2 years after 7nm is in volume production.
yankeeDDL - Wednesday, December 11, 2019 - link
Typo: *10nm in 2020 ...CiccioB - Wednesday, December 11, 2019 - link
The "mammoth" TSMC still has a revenue smaller than Intel.So Intel in not that small and is capable enough to keep their foundries up to date.
Unless some problems occurs like those for 10nm. But if you think that is (ever) Intel managed to get their initial 10nm promises, TSMC would now be 4 years back.
Intel is creating its own 7nm (which are NOT TSMC 7nm) in parallel with 10nm PP.
As said, TSMC can have all the plans they want like Intel has in this slide, but all that counts is HOW the PP is going to work.
Their 20nm where quite advanced with respect to the other foundries, but it was just junk until they adopted FinFET as all the other foundries. At that time they were in par.
yankeeDDL - Wednesday, December 11, 2019 - link
Like I said ... the roadmap looks good. If they can deliver it, they will be in good shape.If.
Competition is good for everybody, so I certainly hope it will be the case, *but*, Intel is the last, or one of the last few companies with their own fab. No matter how big they are, it'll come a moment where it won't make sense, financially. I think we're there, or almost there, and I don't believe they can get to 1.4nm and stay competitive. That's my guess: time will tell.
Korguz - Wednesday, December 11, 2019 - link
any sources for your claims there CiccioB ??CiccioB - Wednesday, December 11, 2019 - link
Which sources for which claims?Korguz - Wednesday, December 11, 2019 - link
the post with mammoth in quotesCiccioB - Thursday, December 12, 2019 - link
And which claims do yo need source for?Korguz - Thursday, December 12, 2019 - link
" Intel is creating its own 7nm (which are NOT TSMC 7nm) in parallel with 10nm PP. " where did you read this from.. doesnt seem to be a mention of this in this article..CiccioB - Friday, December 13, 2019 - link
Huh?Don't you know Intel is already developing its 7nm PP right now?
Or do you think they are going to wait for their 10nm problems to end before starting the development of the new PP?
Just by curiosity, do you know how long it takes to develop a new PP?
Korguz - Friday, December 13, 2019 - link
dont you know how to post a source for your claims ? ie a link or mention of a website.its safe to assume that. but if all the companies that are able to make ICs get the equipment and tools to make them from the same handfull of companies, then for the most part.. the base design would be the same. if they would smart.. intel would be.. cause it could take them 3+ years before its ready.. and that being said.. this roadmap.. is bogus and garbage.. untill intel actually releases products for the given node. do you know how long it takes ???
look.. post links to your claims.. or your claims.. or just that ... yours.. nothing more
Zizy - Tuesday, December 10, 2019 - link
Well, considering 10nm issues I don't trust this plan at all. This backporting sounds ... troubling. Intel surely wishes they didn't have all those 10 nm problems or that at least that their CPUs could be remade to 14 nm process. But at the same time, backporting being an official strategy from now on means Intel doesn't trust their ability to offer great performance, yields or even basic ability to manufacture chips on their upcoming processes.frenchy_2001 - Tuesday, December 10, 2019 - link
Backporting is the (very late) reply by intel to their current manufacturing problems.Any other company would hve back ported their new architecture to their current node once they realized their manufacturing problems.
Not intel. They have been selling Skylake derivatives for 4+ years on 14nm process iterations.
Their new architecture was entirely married with their process node and they have been waiting all this time for manufacturing to catch up.
This backporting shows they are changing the way they design and implement new architecture to *NOT* fall back in that trap. Whether they will succeed is another matter...
Very aggressive road map. We'll see soon if 10nm was a single hiccup or a symptom of deeper problems. (by seeing when and how 7nm releases...)
TristanSDX - Tuesday, December 10, 2019 - link
10 nm is not single hiccup. They had serious problems with 14nm.Spunjji - Wednesday, December 11, 2019 - link
People have already forgotten what a mess the Broadwell "launch" was.Nagorak - Wednesday, December 11, 2019 - link
To be fair, AMD was so far behind until recently there was no reason not to just keep refreshing. Even now, Skylake is still faster for high end gaming due to the clockspeed advantage. AMD is the better buy across most of the product stack, but Intel still has that.Spunjji - Wednesday, December 11, 2019 - link
Intel's not the better buy for high-end gaming - it's the better buy for *high refresh-rate 1080p gaming*. Anybody using VR / ultra-wide / 4K displays with high detail levels in recent games, which is what now constitutes high-end, is still going to be GPU limited.NirXY - Wednesday, December 11, 2019 - link
Just because GPU's are limiting us today, doesn't mean they will still be as much next gen.anonomouse - Tuesday, December 10, 2019 - link
Considering this is a conference on device(transistor) technology and a slide deck presented by a device(transistor) research and manufacturing partner, does backport here really mean what people here are hoping it means?i.e. are they potentially talking about back porting transistor/wire layouts and optimizations (metal stacks, Via materials, etc) to slightly older process nodes
Ian Cutress - Tuesday, December 10, 2019 - link
There is an element of that, a sort of cooperative DTCO between techniques to help improve older process node technologies. However as the graph shows, the new node is derived from the first gen of the previous node, so how much can be back-ported on the litho side is perhaps questionable.anonomouse - Wednesday, December 11, 2019 - link
They've definitely done things like this in the past. For example, 22FFL took the transistor fin from their 14nm, brought a modified version of a 14nm SRAM cell to 22FFL as the HCC SRAM, and those are just the things they publicly talked about. I'm sure there are other things they could bring over as well, like adaptations in the via/metal layers with new materials or modified double-damascene etc etc etc.What I think everyone here is jumping to for 'backporting' is assuming this means Sunny Cove or Willow Cove etc being brought a process node. Nothing in any of these materials suggests that at all.
versesuvius - Wednesday, December 11, 2019 - link
Roughly speaking (n) nano meters is still the same no matter what technology is used to make it (i.e. same transistor count per area, hence the same power use). It will mean better yields, which in turn means lower supply of low end chips (i3, pentium, celeron) and some low volume weirdos. Improving architecture and design is a different matter, which until now was not called backporting but it is now.peevee - Tuesday, December 10, 2019 - link
Somebody please sue them all for the fraudulent names.milkywayer - Tuesday, December 10, 2019 - link
There should be jail time for such BS but it should apply to the top management. Enough of these fake nm and fake unlimited cell phone plans.CiccioB - Tuesday, December 10, 2019 - link
The backport opportunity just shows a underline problems of the future PPs: costs.Complexity and design costs will just have an great impact on the choice of the PP to chose, and seeing that since 22nm transistor/cost curve has turned negative, it is even possible that for the next PPs, when you are not forced to use the latest shiny expensive new PP for performance/consumption issues, you may get cheaper designs using older PP.
MCM designs will also help in reducing the needs of smaller transistors at all costs.
candre23 - Tuesday, December 10, 2019 - link
It's a bit of a stretch to claim that they're "already on" 10nm, considering they've only managed to actually ship a handful of mobile parts on that process node. Intel has been stuck on 14nm for nearly six years and is *still* struggling to manage decent enough yields on 10nm to actually sell them. Are we really to believe that they're capable of a node shrink every other year - especially when each further shrink is going to be harder than the last?This is just intel trying to salvage some industry faith after getting hammered by AMD for the last couple years.
nevcairiel - Wednesday, December 11, 2019 - link
10nm was broken, but 7nm is an entirely different process using EUV. As long as they kept development of it active, the 10nm problems should not really impact it.7nm EUV is realistically easier to do then the 10nm process, since EUV solves many of the problems that a small DUV process had to overcome.
Santoval - Wednesday, December 11, 2019 - link
EUV is not exactly the holy grail of photolithography. It solves plenty of DUV's problems (largely because the much tighter wavelength can let fabs etch patterns in just one step instead of 2 to 4 steps) but it has its own set of problems : high LER (Line Edge Rougness) of features, the step & scan machines have much lower energy efficiency (resulting in quite higher energy bills) due to much higher losses of EUV light from the source to the target, the optics need to be orders of magnitude more precise and are thus (also) far more expensive, and more or less the same applies to the masks and their pellicles, both of which need to be highly reflective (at least 85 - 90%).In short EUV is a much more delicate, elaborate, and *far* more expensive business than DUV, which my guess is what forced GloFo to bow down from the EUV game. Intel, TSMC and Samsung have the monies to invest in EUV R&D and build EUV fabs with many ASML's EUV scanners, but I strongly doubt anyone else can do it. As for manufacturers of EUV scanners ASML will almost certainly remain the only company in the world in the future as well. Their monopoly naturally allows them to charge whatever they think the trio of companies above can afford to pay, nothing less and nothing more.
CiccioB - Thursday, December 12, 2019 - link
AFAIK, EUV is more expensive for each mask, but it requires less masks than DUV.That's why TSMC 7nm+ PP is looked for lowering production costs and raise the yields, as all those multiple patterning processes will no be needed anymore.
Probably he big drawbacks of EUV is that is is slower to produce. So it needs more scanner, or faster more expensive ones. And that's also why EUV is not applied to all layers in its first version, but only on the critical ones that on multipatterning raise DUV costs and lower yields..
Everett F Sargent - Tuesday, December 10, 2019 - link
Considering Intel's roadmap. Has Intel released 10nm silicon in the desktop, workstation or server space yet? AFAIK, the answer is a resounding NO!When/if Intel does 10nm in those spaces (say 2020) will they be at lower GHz then the latest 14nm silicon due to heat issues (e. g. by not adopting a chiplet strategy and going with a monolithic single chip strategy in the face of heat issues)?
I seriously doubt yield issues at 10nm, simply because Intel has had five (going on six) years to solve that issue.
I guess what I'm trying to say is that Intel did not learn from their own previous history of chasing GHz. That Intel has pushed GHz at the 14nm node at the expense of the 10nm node. In other words, if 10mn is slower than 14nm who would buy 10nm? Assuming that core counts (needs to go up), power (needs to go down) and pricing (needs to go down) don't change significantly.
It will be like six years for 10nm desktop silicon. What's up with that?
haukionkannel - Wednesday, December 11, 2019 - link
Intel will most likely jump directly to 7nm in desktop parts. Their 10nm is not good for desktop usage... and maybe newer will be.ksec - Tuesday, December 10, 2019 - link
1. Those date ( year ) are all Q4, and volume isn't in the quantity we traditionally expects, so unless they could push 7nm faster, it may be better to shift expectation or general conciseness of year by 1. Effectively 7nm is 2022, and 1.4nm is 2030.2. I was surprised the article has no mention of Jim Keller, this method of delivery and back porting or design and node detachment is called train delivery in Apple or AMD. Something he mentioned in the Anandtech interview.
3. The three stage manufacturing method is also basically the same as TSMC, N7, N7P / + and N6, with three iteration of each node. ( EUV being exception )
4. If Intel has fixated its 5nm on High NA EUV they will be repeating the same 10nm mistake again. Not only do I doubt ASML will have those machine on time, delivery of it will also be extremely limited. If I remember correctly ASML only delivered single digit of their EUV during first year, ~20 during 2nd. And in case Samsung is not trying to grab everyone of them, HVM on first year of introduction sounds like a very risky move.
5. Still wish some industry perspective on economical model, although the recent Semienginnering revision of 3nm cost down to Sub $2B seems like a big improvement, it is still the elephant in the room.
Adonisds - Tuesday, December 10, 2019 - link
Assuming each future Intel node increases density by 2x and each TSMC node by 1.7x, then Intel 1.4nm should be equivalent to TSMC 600 picometersDannyH246 - Tuesday, December 10, 2019 - link
Why would anyone believe a word Intel says about anything now? They have LIED for years about 10nm - how many times have we heard that 10nm is now “shipping”. They have LIED for years regarding security and shipped countless processors with serious vulnerabilities that they knew about. And now AGAIN they are LYING about benchmarks. Such a deceitful and dishonest company.TEAMSWITCHER - Wednesday, December 11, 2019 - link
Please... spare us your righteous indignation.DannyH246 - Wednesday, December 11, 2019 - link
Plenty of people on here alluding to the same thing i said. Intel are an untrustworthy company with a long history of lies and deceit. Deal with it fanboy.TristanSDX - Tuesday, December 10, 2019 - link
lol, back-porting as part of strategy, they are preparing for more 10nm like delays, interesting learninglet they introduce back-tick, back-tock philosophy
eva02langley - Tuesday, December 10, 2019 - link
Sure... and I am the ruler of the world...eva02langley - Tuesday, December 10, 2019 - link
The problem is as of today, Intel is having their biggest competitor rising in an incredible fashion... not AMD... TSMC. I am betting on TSMC to keep the lead.outsideloop - Tuesday, December 10, 2019 - link
Who do you trust more in 2020 and beyond to hit node goals? TSMC or Intel?Spunjji - Wednesday, December 11, 2019 - link
Neither. TSMC dropped the ball on 32nm (cancelled the node late, leaving both GPU and mobile chip partners high and dry) and fumbled it on 20nm (power characteristics were so bad that they probably should have cancelled it; again, GPU partners notably skipped that one).Intel have historically been better, but 14nm was a mess and 10nm is an absolute travesty. I'm not sure it makes sense to assume they'll continue in the same vein, but obviously we can't just rely on their statements to the contrary after 4+ years of "10nm tomorrow".
In summary, the solid bet is that they'll both make a few questionable decisions that will hold up their process technology have wider impacts on the industry. Anything more specific than that is speculation.
CiccioB - Thursday, December 12, 2019 - link
This.People easily forget history for their convenience or due to ignorance.
We are now in a situation where Intel has failed a PP step, while TSMC was successful but did not make great things either. They just anticipated everyone that decided to use 7nm with EUV.
We will see how things will be when Samsung and Intel will come out with their EUV PPs.
That's the joint point where to do comparisons and see who will suffer.
Korguz - Thursday, December 12, 2019 - link
" People easily forget history for their convenience or due to ignorance." yes they do. like the shady dealings, theats and bribes intel made to shut amd out of the market, or the constant lies about 10nm being on track, the criticism AMD got for its power usage before Zen with their chips, but now that intel is using more power for theirs, it seems to be ok... etc etc etcsor - Tuesday, December 10, 2019 - link
This seems like a shrewd plan, they’re hedging with this parallel feature size plan. Basically they can choose to release a new CPU on either a new node or the ++ size, depending on what is developed enough to work.Everett F Sargent - Wednesday, December 11, 2019 - link
This article was published three months and 22 days too early.werpu - Wednesday, December 11, 2019 - link
Marketing papers are quickly written to keep the stock holders calm. It is either deliver or shut up...Koenig168 - Wednesday, December 11, 2019 - link
Amazing!!! Amazing that someone will actually take this 2 years cadence seriously.stephenho - Wednesday, December 11, 2019 - link
In 10 years 2029, Intel will file for chapter 11 .... they will be in 10++++ for a long long time, that is what intel does best, to fine tune a process. If AMD/TSMC is talking about anything beyond 3nm, I will sell all my AMD shares. I do not believe in anything smaller than 3nm yield will be in big big trouble.haukionkannel - Wednesday, December 11, 2019 - link
Noup... 10nm will die as soon as 7nm euv start mass production... their 10nm will newer be any good.Machinus - Wednesday, December 11, 2019 - link
Unless Intel ships 10nm processors in the next 3 weeks, this slide is just pure lies.nevcairiel - Wednesday, December 11, 2019 - link
10nm CPUs are already shipping in products on shelfes right now. But people don't like to accept the Ice Lake mobile systems, apparently.drothgery - Wednesday, December 11, 2019 - link
There's a bizarre thing on enthusiast web sites where many people seem to think desktops are the only important market segment for PC CPUs instead of the least reality where the only way you can argue they aren't the least important market segment is because of halo effects.Machinus - Friday, December 13, 2019 - link
It isn't bizarre at all. Those websites are correct. If you aren't selling desktop, hedt, and server processors on the same node as your competitors, it's because you failed in R&D and you can't produce them at all. You might be the last person on Earth who didn't know that AMD is having the biggest year in it's history, and it's not because of irrelevant laptop chips. Try reading a newspaper.nils_ - Thursday, December 12, 2019 - link
They also sold cannon lake products back in the day, though it was also mostly DOA. And there is no H Series Ice Lake for mobile workstations. Pretty limited product stack from my perspective.Santoval - Wednesday, December 11, 2019 - link
Let's do a naive and rough calculation of the projected transistor density of Intel's 1.4nm node.Intel's 10nm node has 100 million transistors per mm^2 (MTr/mm^2), which provides a nice round base for the calculation. Assuming Intel retains a doubling on average of transistors with each of their number nodes, their 7nm node will 200 MTr/mm^2, their 5nm node will have 400 MTr/mm^2 ... and finally their 1.4nm node will have 3.2 *billion* transistors per mm^2.
That is almost certainly physically impossible, so Intel might rather add +80% more transistors on average with each number node. That still means ~1.9 billion transistors per mm^2 at 1.4nm. A +70% extra transistors on average means ~1.4 billion transistors at 1.4nm. I have no idea if that is feasible, but Intel will probably be even less aggressive, maybe by adding +60% extra transistors on average until 2029 (or, much more likely, 2035), which would result in ~1 billion transistors per mm^2 at 1.4nm.
Even so, that would be the end of the road for transistors, unless new materials provide a speedup at lower densities.
Santoval - Wednesday, December 11, 2019 - link
p.s. My calculation employs as a base Intel's high performance 10nm node, which has the highest transistor density. That's the node with the ~100 MTr/mm^2. Intel has two other 10nm nodes though, one for moderate performance (moderate density) and one for lower performance/density. I cannot recall precise numbers but I think the moderate performance 10nm node (which, to my knowledge, is what Ice Lake-U/Y SoCs are fabbed on) has a density around 80 MTr/mm^2 and the lower density 10nm node has 55 to 60 MTr/mm^2.I did not take into account these other two nodes because the calculation would become quite more complex. Intel's high density 10nm node is intended for -H & -S desktop CPUs (which do not exist and apparently will not exist in the entire 2020 either, due to poor yields) and Xeon CPUs.
Llawehtdliub - Wednesday, December 11, 2019 - link
Intel shareholders in this comment section.Just sell boys. Their stock is going to take a big hit Q1 2020.
bananaforscale - Wednesday, December 11, 2019 - link
Given the 14nm+++++++++++++++ mess I'm not holding my breath wrt that timeline being accurate.shabby - Wednesday, December 11, 2019 - link
Is it April fools already?Everett F Sargent - Wednesday, December 11, 2019 - link
There is a typo in the headline ,,,"2019 to 2029"
should be ...
"2019 to 2119"
PPere - Wednesday, December 11, 2019 - link
Naaaaa for sure they will invent the +++++ and the ++++++++++ and more the +++++++++++++. And probably in 2245 they will reach 5nm.fizzypop - Wednesday, December 11, 2019 - link
I am surprised they never thought to try for 12nm although at this stage it probably is almost identical to 14+++. I wonder if TSMC and Samsung are using ASML or are they with some one else for equipment. I REMEMBER the Intel are shareholders of ASML and have burnt bridges so can not go with some one else. Maybe the issue is with the 1st Batch of ASML equipment and Intel do not want to retool.nevcairiel - Wednesday, December 11, 2019 - link
Noone has really done a "12nm" node, its just another name. What Intel calls 14+++, you can get from eg. TSMC as a 12nm process - a refined 14nm process.Kamus - Wednesday, December 11, 2019 - link
ROFL. 1.4 nm... they can't even sort out 10 nm after a 4 year delay, and they expect people to believe they'll ever go beyond 7 nm?UltraWide - Wednesday, December 11, 2019 - link
Cool story intel, now ship product!jiffylube1024 - Wednesday, December 11, 2019 - link
So hang on, let me get this straight. Intel is stuck on 14nm for the desktop, with 10nm mobile chips trickling through the pipeline. Yet now, somehow, after being stuck on 14nm for 4 years, Intel will squeeze in 5 MORE node shifts after 10nm in the next 9 years!?MattZN - Wednesday, December 11, 2019 - link
The slide is meaningless. It's a pie-in-the-sky presentation, not anything based on engineering work that is actually in-progress. That should be obvious given how many years it projects ahead.-Matt
CHLIAO - Thursday, December 12, 2019 - link
likes TWN's president candidate's announcement : Fa Da CaiDr.GarbageNode - Friday, December 13, 2019 - link
I am rooting for Intel for the sake of competition in the space, better products at better prices for the consumer and generally moving technology forward. The resurgence of AMD is in my mind the best thing that has happened in this space in a very long time. If Intel can get their company in order and make a comeback with competitive products, that would be a new golden era. That said, this looks overly optimistic from Intels side. I'd be very surprised if they can execute on that cadence. Their history does not speak for them either.Korguz - Friday, December 13, 2019 - link
rooting for intel for the sake of competition ?? considering they stagnated the cpu market for 3 or 4 years... no thanks... better to root for amd... at least they are doing something to move the cpu market forward.. more so then intel hasnn68 - Friday, December 13, 2019 - link
More announcements? Gee, I'm gagging. XDCeToBe - Friday, December 13, 2019 - link
IntelThe presentation in the slide of the future should at least better be called: In more we trust. That is of course meant for the interested parties, who have lost trust. For Intel to get it back, the slide will be contra-productive.
Building on an old prophecy and no longer valid law(s) is not the way to do it. Better is to express a new mission and goals and then a strategy to obtain these. The setup should be built on frontier-science, technical possibilities, ecological and economical aspects as well as political considerations.
It is doubtful that anyone these days can give a reasonably reliable outlook for the node in 2029. It’s is furthermore questionable if the node is the most trust-giving characteristic of the forthcoming products.
ASML
The slide of ASML gives even more ashtonishment. Is it the mother of all slides or a child?
If a derivate, are there no other clients of ASML with other slides?
Commercially not a good move.
BACK TO THE FUTURE
If the slide is a kind of attempt to influence the future. Expect some new ones in this theatre soon.
croc - Monday, December 16, 2019 - link
What I REALLY want to see is a 5 year roadmap of Intel's chipsets. CPUs are nice and all, but the real meat is what they run on. Hopefully the good Dr. can make this a priority, right after he looks at my knee...:-)Revv233 - Sunday, December 29, 2019 - link
Personally I wouldn't mind seeing ice lake running @ 5ghz on 14nm with it's 18% IPC gain. Maybe that's not good for the future of cpu short term but would be the fastest chip around in a long time.At some point all chip manufacturers will have to take a long look at IPC as they will no longer be able to brute Force advancements out of process nodes.
Feels a lot like the netburst days all over again. The mobile cores are running lower clocks at lower speeds less power consumption with most of the performance still there.
Anyone remember when the adapters to convert laptop chips to desktop motherboards were around? Led benches for over a year before Intel launched the core models.
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wow&wow - Monday, June 1, 2020 - link
"IN MOORE WE TRUST"IN MOORE WE FAILED :-)
"a slide is worth 1000 words"
A chip is worth 1000 slides.