> The downside of these SoIC technologies however is that the stacked design has to be co-designed with each other
I would disagree that this is a downside. This is no different than providing a footprint for PCB manufacture or microbumps on an interposer. It's a lot more detail, sure, but as long as both companies are comfortable agreeing to that shared interface, it's no big deal. Worth noting that TSMC has the ability to act as the intermediary here to protect trade secrets and the like. There's also no issue here if the entire stacked design is provided by the same vendor. Storage and RAM folks will love this.
There is a penalty in design time - the interconnection layout has to be decided before either chip design can be finished. When an interposer is used however, the interconnection layouts and chip layouts of both chips can be done independently and the interposer matches the chips together - if one chip is later altered then only the interposer needs to change. As the interposer is basically a much shrunk PCB done on an old silicon process (65nm) it is far easier to change than a complex piece of logic done on an advanced process.
Because SoIC has metal layers projecting /through/ the dies, it needs dedicated die design for that packaging method. You can't just design an interface surface, because all your die logic needs to shuffle around the metal pillars.
I have a BS and MS in Computer Engineering and I've done some pretty decent-sized hand-layouts (~700 transistors on 180nm). The pillars are an inconvenience, but they aren't really any different than designing for pads in a QFN package, wafer-level-packaging (WLP), or microbumps with a uniform grid. It's even less of an issue with how much we rely on synthesis tools to do the routing nowadays. The key advantage that TSMC is offering is a 0.9 um pitch (vs 25 or 40 um for backend) which lets you have a much smaller area for the same number of connections, making routing even easier for logic chips or density higher in the case of memories.
That said, there's no reason why every layer of the stack would need to have the same set of columns or even have all of them traveling all the way through. That's useful for things like memories where a 3D crossbar is easy to implement and where you can save on economies of scale, but it's not required. You could also add an extra "adapter" layer to the stack to route from one interface to another if chips have different interfaces.
It's never been exactly clear what InFO actually /is/. From the marketing side, it just looks like putting an extra substrate layer or silicon interposer on the package, but is for an unknown reason given a different name. For example, you have both CoWoS-L and InFO-LSI, both of which are a set of dies stacked on a silicon interposer stacked on a substrate, but with no clear indication of why the two are different.
CoWoS handles larger devices (just under reticle up to multiples of reticle). InFO is for smaller devices, up to reticle and no larger.
To me it looks like to some extent they're solving the same problem: "I want to place two chips side by side". But once you actually try to solve that problem many questions arise: how fast does the connection need to be? how much heat dissipation? how much area? etc etc. Less demanding versions of these answers (think cell phone) allow for one specific way of solving the problem which is cheaper but less performant and can't scale up (InFO); if that's not good enough you can alternatively use the more expensive CoWoS.
How EXACTLY are they different? As far as I can tell the most significant difference is that the physical layer carrying the RDL is organic for InFO, as opposed to Si for CoWoS. Organic means you can flow it then bake it -- easier and cheaper than dealing with super-thin pieces of Si as you need to for CoWoS.
TL;DR TSMC can solve your 2.5D needs, whether they are cheap and low power (eg watch/phone) or expensive and high power (eg discrete GPU).
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SaberKOG91 - Wednesday, September 2, 2020 - link
> The downside of these SoIC technologies however is that the stacked design has to be co-designed with each otherI would disagree that this is a downside. This is no different than providing a footprint for PCB manufacture or microbumps on an interposer. It's a lot more detail, sure, but as long as both companies are comfortable agreeing to that shared interface, it's no big deal. Worth noting that TSMC has the ability to act as the intermediary here to protect trade secrets and the like. There's also no issue here if the entire stacked design is provided by the same vendor. Storage and RAM folks will love this.
Duncan Macdonald - Wednesday, September 2, 2020 - link
There is a penalty in design time - the interconnection layout has to be decided before either chip design can be finished. When an interposer is used however, the interconnection layouts and chip layouts of both chips can be done independently and the interposer matches the chips together - if one chip is later altered then only the interposer needs to change. As the interposer is basically a much shrunk PCB done on an old silicon process (65nm) it is far easier to change than a complex piece of logic done on an advanced process.SaberKOG91 - Wednesday, September 2, 2020 - link
Right, but TSMC can short-cut this by setting the interfaces for both vendors.edzieba - Thursday, September 3, 2020 - link
Because SoIC has metal layers projecting /through/ the dies, it needs dedicated die design for that packaging method. You can't just design an interface surface, because all your die logic needs to shuffle around the metal pillars.SaberKOG91 - Friday, September 4, 2020 - link
I have a BS and MS in Computer Engineering and I've done some pretty decent-sized hand-layouts (~700 transistors on 180nm). The pillars are an inconvenience, but they aren't really any different than designing for pads in a QFN package, wafer-level-packaging (WLP), or microbumps with a uniform grid. It's even less of an issue with how much we rely on synthesis tools to do the routing nowadays. The key advantage that TSMC is offering is a 0.9 um pitch (vs 25 or 40 um for backend) which lets you have a much smaller area for the same number of connections, making routing even easier for logic chips or density higher in the case of memories.That said, there's no reason why every layer of the stack would need to have the same set of columns or even have all of them traveling all the way through. That's useful for things like memories where a 3D crossbar is easy to implement and where you can save on economies of scale, but it's not required. You could also add an extra "adapter" layer to the stack to route from one interface to another if chips have different interfaces.
Alexsuns - Wednesday, September 2, 2020 - link
It's useful information. I think it'll be popular.name99 - Wednesday, September 2, 2020 - link
Thanks for this summary, Ian! For some time I've been looking for an overall summary of TSMC's tech in this area.edzieba - Thursday, September 3, 2020 - link
It's never been exactly clear what InFO actually /is/. From the marketing side, it just looks like putting an extra substrate layer or silicon interposer on the package, but is for an unknown reason given a different name. For example, you have both CoWoS-L and InFO-LSI, both of which are a set of dies stacked on a silicon interposer stacked on a substrate, but with no clear indication of why the two are different.name99 - Thursday, September 3, 2020 - link
CoWoS handles larger devices (just under reticle up to multiples of reticle).InFO is for smaller devices, up to reticle and no larger.
To me it looks like to some extent they're solving the same problem: "I want to place two chips side by side". But once you actually try to solve that problem many questions arise: how fast does the connection need to be? how much heat dissipation? how much area? etc etc.
Less demanding versions of these answers (think cell phone) allow for one specific way of solving the problem which is cheaper but less performant and can't scale up (InFO); if that's not good enough you can alternatively use the more expensive CoWoS.
How EXACTLY are they different? As far as I can tell the most significant difference is that the physical layer carrying the RDL is organic for InFO, as opposed to Si for CoWoS. Organic means you can flow it then bake it -- easier and cheaper than dealing with super-thin pieces of Si as you need to for CoWoS.
TL;DR TSMC can solve your 2.5D needs, whether they are cheap and low power (eg watch/phone) or expensive and high power (eg discrete GPU).
Corrections welcome!