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  • Shaunathan - Wednesday, May 31, 2023 - link

    Incredible thanks for the update Anton!
  • del42sa - Thursday, June 1, 2023 - link

    "TSMC's N2P fabrication technology that will enter HVM in late 2026 or early 2027"

    so they slow down while price skyrockets
  • Kevin G - Thursday, June 1, 2023 - link

    The raw physics at this scale is hard and the slow down of new process nodes has generally been expected across the industry.

    The pricing side is more debatable as the factories to produce these chips is around $10 billion USD. That does need to be recovered by wafer sales. Could TSMC likely sell their capacity for less while remaining profitable? Likely as any good business with a high demand product/service always has a good margin. Could they charge that they did for previous process nodes and still make money? Not so much as fab costs have gone up tremendously. Beyond this is also developing newer process nodes which the R&D only gets more difficult and expensive.
  • back2future - Thursday, June 1, 2023 - link

    [Few have answers to societies development (and their hardware needs) with saturated markets and reduced offerings for (cost reduced) upgrading or upcycling rewardings. Their concurrency on global markets is spendings for essential needs and every day living costs. If 'a science genius' could/would reduce production cost for new nodes it's probably distributed within all business hierarchies.]
  • jjjag - Friday, June 2, 2023 - link

    A semicondutor Fab of the most state-of-the-art technology has not been as low as $10B in many years now. 5/3nm Fabs cost at least $25B now, and looking ahead to 2nm and 1.4nm with more EUV layers, figure $30-40B in 10 years. Manufacturing $$ is increasing exponentially, and the ONLY way to mitigate that cost is to design smaller and smaller chips and use more advanced packaging techniques to build up an SOC. So all foundries are spending more and more on advanced packaging techniques to go along with the silicon technology itself.

    To reduce overall system/platform cost, you must increase the level of integration. CPU+chipset+NIC+GPU+FPGA on the SOC greatly reduces system cost (as it has been for the last 20 years), even though the individual pieces of silicon cost more than they did at the last node.

    So foundries need to keep increasing their price to produce the individual pieces of silicon to absorb their increasing costs, but offer these advanced techniques to provide overall value at the system level.
  • shabby - Thursday, June 1, 2023 - link

    Aaaaaand it's gone, apple bought all the capacity.
  • back2future - Thursday, June 1, 2023 - link

    ["Apple's target audience consists of middle-class and upper-class users who can pay higher for products that provide them with an incredible user experience. This means that these users have a higher disposable income and are willing to pay more for as high-priced products as Apple's."
    "Apple customer demographics include people aged 18 to 45. They are either single, married with no kids, or married with young children or teens. The Apple target audience skews strongly female, with around 66% female to 34% male customers. Among Apple primary customers, you'll find less older or retired individuals."
    "What is Apple's fastest growing business segment? Services was the fastest growing segment in 2022 with a 14% increase in revenue. Apple's Services segment has also been the fastest growing over a five year period."
    "From September 2021‒2022, net iPhone sales contributed 52% of the company's total revenue, dwarfing revenue from other products including the Macbook, Apple Watch, Airpods, and services. Services (Apple Music, TV, iCloud etc.)"]
  • iphonebestgamephone - Thursday, June 1, 2023 - link

    Why do you use chatgpt for every reply?
  • back2future - Thursday, June 1, 2023 - link

    [please define 1) chatgpt 2) every 3) reply; me thinks Apple does a lot of customer categorization for business, technology and brand value optimizations, these citations are examples of common available data summaries (from customers interactions probably), another would be "The typical Apple customer profile is of middle to high economic status, enjoys the small luxuries in life, and appreciates technology and design.", so mass market for energy efficiency impact is not that part of this market (for global high volume numbers of devices and networking bandwidth demand with high performance products, but given Apple devices are higher efficiency networking/media devices on client side]
  • iphonebestgamephone - Thursday, June 1, 2023 - link

    Huh its acrually really cool!
  • James5mith - Thursday, June 1, 2023 - link

    "N2 is a great fit for the energy efficient computing paradigm that we are in today,"

    Hahahahahahahahahahahahahahahahahahahahahahaha

    Energy efficiency has gone completely out the window these days. Core i5's need 150w of cooling now, and don't have much better performance than the old 65w variants from a few years ago.
  • m53 - Friday, June 2, 2023 - link

    "TSMC's N2P fabrication technology that will enter HVM in late 2026 or early 2027"
    That is a minimum 2 year after intel introduces it with 20A and 18A. So it looks like Intel is really taking their manufacturing crown back. Of course it depends on whether Intel can really bring 20A by the end of 2024. But the recent comment from Nvidia CEO suggest they might.
  • my_wing - Wednesday, June 14, 2023 - link

    TSMC N2P Backside is not equal to Intel PowerVia (20A). If Intel 20A is there by end of 2024 with GAA and PowerVia in place. Intel 20A > TSMC N2P in performance and density.

    If you look at the Intel slide, and this article just use the term to confirm my thinking "Backside Power Rail" (without mention nTSV), that TSMC N2P is 1st Gen Backside Power Delivery while PowerVia is 2nd Gen Backside Power Delivery, the Intel Paper shown PowerVia is Backside Power Rail + nTSV.

    Basically, you see this way (think you are having a sandwich) .... M1(logic), M0, M1(power) ....; Backside Power Rail is that the copper wire goes through M1(power) to M0 to M1 (Logic) then like traditionally, the power still goes to logic side; PowerVia supplier the power from the back directly through the nTSV. TSMC like to take small steps at a time. So if Intel 20A delivery what is it then Intel is at least 1 full node ahead, just like the old days, it can be good or bad as intel has a history of milking the cow (toothpaste style again).
  • Oxford Guy - Sunday, June 4, 2023 - link

    How many nanometers is '2nm'?
  • my_wing - Wednesday, June 14, 2023 - link

    7nm is N3 class.
    Then if you are asking why intel used ++++
    TSMC N2 is 7nm++++++++++++++++++

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