I'm curious what the overall E-core performance is going to look like since the cluster won't have L3 cache access. Chips and Cheese did some analysis of the LP E-cores on MTL and found this specifically to be a big negative. I'm guessing this design is going to be limited to just LNL and is predominantly for the power savings.
Interestingly, Intel is comparing Skymont to Raptor Cover. I agree that we have to wonder how the L3 (or lack thereof) affect this, but from the Chips and Cheese figures alongside Intel's performance improvement figures, it looks like Skymont without L3 cache will be faster than Crestmont with L3 cache.
That's my assumption as well as I think the GPU would be the other part predominantly using it and they shouldn't really both be hitting it at the same time.
Side cache is not the same as L3, or I think they would have called it that. shared L3 is where the memory sync can happen across cores. if not, it needs to go all the way back to ram. So, side caches really cannot be considered as L3, more like expanded L2 for E-core and expanded l3 for P-Core? is my guess. Yes, it means things that run on both E-Core and P-Core, at the same time, will take a hit on performance. I think they were targeting the majority use case. where most won't need more than 4 threads or threads won't be working on the same data.
It absolutely will. Because this is going to be slower than meteor lake in CPU. Elite is supposed to be 30% faster. Intel should have released 8 P-core version to compete in performance. But I think they wanted to reserve that to be produced on their own fabs.
Snap Elite is supposed to be 30% faster at essentially-undisclosed power. Lunar Lake will ironically undercut the Snapdragon Elite on power and cost while delivering good performance.
I hate to ask this, but was this article fully written by Gavin and proof'ed by another editor? Was there a deadline push to get it out as soon as Intel released the information on Lunar Lake? It just reads so, so disjointed. It feels like there are so many issues in this paragraph alone on the P-core overview; it feels jarring to read.
"This Lion Cove architecture **also aligns with performance increases**, boasting a predicted double-digit bump in IPC over the older Redwood Cove generation. This uplift is noticed, especially **in the betterment of its hyper-threading, whereby improved IPC** by 30%, dynamic power efficiency improved by 20%, **and previous technologies, in balancing**, without increasing the core area, **in a commitment of Intel to better performance**, within existing physical constraints."
I've seen so much better work from Gavin, and Anandtech in general, that I almost hope that this page was heavily written by software. I know it's a press release, and there's not a whole lot of information, but the level of first party detail here feels similar to the Architecture Day 2021 presentations Intel did on Alder Lake, which got fantastic coverage from Andrei and Dr. Cuttress, and here it feels like we are getting a poorly worded restating of the slides with hardly any analysis or greater than surface level understanding.
I've been reading Anandtech since I was 15, and the level of detail in the Sandy Bridge era articles honestly had a huge influence on my choice to pursue a career in CPU Design. I've mountains of respect for what Anandtech has published in the past, but this article feels rushed.
Thank you for responding. I hope there’s an opportunity to address some of the writing at a bare minimum and maybe inject some of your own voice.
Lunar Lake honestly looks like a pretty big deal. The process is great, the microarchs seem impressive on paper, and it’s coming out to market within a quarter of when it needs to, not within three years. Looking forward to deeper analysis and comparisons, wherever they come from, when the time comes.
A deadline for what? To regurgitate Intel PR hype as an LLM enhanced unreadable English as a second language article before everyone else publishes their copy of Intel’s Press Release? This article should have never been published. The Xe2 page is particularly horrendous.
Now, I also like good copy editing, but this kind of coverage is done almost in real time. That, plus the time zone difference makes it hard to have a fully copy-edited and proofed article posted, all within hours of the presentation.
I understand that. Anandtech has done it in the past, and produced really stellar coverage that way. I'm a little surprised that some of the paragraphs haven't gotten complete, proper rewrites more than 36 hours after the article went live. (To be fair, that's one business day really). But it's a headliner article on their front page; I'd hoped for more love.
Thank you for writing this out. Similar feelings, but I could not have put it so well. Here’s hoping AnandTech can figure out how to get back to that level of quality.
Yeah, it definitely comes across as two-faced for Intel to be pitching its foundry business to others, while it's not even using it for its own cutting-edge CPUs!
1) bob (or brian?) made a deal with tsmc and they need fill the required capacity
2) tsmc chiplet packaging requires all tiles to come from tsmc (but mixing tile foundries is fine as long as someone else packages)
3) lunar lake isnt high power high core desktop/server, there's plenty else to make themselves, and obviously they've been ramping cutting edge future nodes
4) these things take years, why would a recent subsidy relate to old deals
> 1) bob (or brian?) made a deal with tsmc and they need fill the required capacity
This is probably the dumbest claim I've seen in a while. There's guaranteed to be an escape clause in that contract, although Intel would be stuck with some fee.
Given the current demand for cutting-edge nodes, I'm sure Intel could probably work out an agreement with another fab customer to buy their excess wafer capacity and probably even turn a profit by it.
> 2) tsmc chiplet packaging requires all tiles to come from tsmc
Second dumbest claim in the thread. Lunar Lake uses Foveros, not TSMC's technology, and Intel is making the base layer on their own 22 nm node.
> 3) lunar lake isnt high power high core desktop/server
What does that have to do with anything? It still needs to compete on performance and efficiency!
Intel's foundry service doesn't have a full suite of nodes to choose from and is currently building out a fabs. In the meantime, client will be using some of the TSMC N3B allocation that Intel carved out years ago. Expect 2024-2025 to be peak TSMC usage.
What other options were realistically available? Intel 3 is just hitting the market and fully allocated to Xeon 6 initially. Intel 4 isn't library complete and wouldn't work for a tile that also contains NPU and GPU. Intel 7 is heavy DTCO'd for ADL/RPL and has poor low wattage performance. 18A isn't ready yet.
By the time 14A releases, Intel will have a selection of 18A and the Intel 3 family of nodes to pick from for their other CPU tiles.
> Intel 3 is just hitting the market and fully allocated to Xeon 6 initially
The Lunar Lake CPU tiles can't be very big. They should've been a good "pipe cleaner" product for Intel to ramp up their "3" node, before making the huge Xeon dies.
I hadn't noticed the GPU was on the same tile. If true, I think they could've kept it on its own tile, as Meteor Lake did.
Intel has not shipped an Xe product on an Intel process since DG1. We don't know that it ports.
Adding a separate die might have increased the package size, and part of the point of this product was to be a small package that could supplant Qualcomm designs easily (and the PMIC callout was specifically targeted at vendors that got burned by Qualcomm's power shenanigans, if you believe Charlie).
yeah, it's not a great look on the fab side, but honestly I hope it's an amazing chip and worth upgrading. I hope Qualcomm's chip is great as well and get some actual innovation/competition going on.
The way I see it, the only defense Intel has for comparing Skymont to the LP Crestmont cores is to defend their decision not to include a separate LP version of Skymont, in Lunar Lake.
In fact, I'll bet what happened is that someone internally made this pitch and the marketing goon who produced the public-facing slides for Lunar Lake opted to reuse that data, since it made Skymont look even better (it's already quite impressive)!
The MTL E cores shared a ringbus with the P cores. The LNL E cores are completely separated from the P cores and function much more similarly to current LP-E cores
AMD doesn't build a package that competes with this product. If Intel delivers with Xe2 (and there's no reason to believe they will, to be clear), this product would win the entire handheld gaming category for the generation in about 30 seconds flat. Lunar Lake wouldn't actually be impossible to stuff into a phablet-style phone, though it obviously wouldn't be easy.
what about the i9-14900KS test redo with Intel Default settings? You told us 20 days ago that you'd redo them :
Gavin Bonshor - Friday, May 10, 2024 - link Don't worry; I will be testing Intel Default settings, too. I'm testing over the weekend and adding them in.
Unless I'm mistaken, the charts don't seem to have changed, and include only a single set of data (without the Intel Default Settings). The text doesn't suggest they were, though I didn't read the whole article again, I admit.
Seconded, also... "Gavin Bonshor - Tuesday, May 21, 2024 - link Hey, thank you for saying that. They are coming as soon as I can get the data updated. I had to fly out to the USA last Monday evening, and the testing wasn't finished in time. I also don't typically work weekends, but I made an exception in this case. I'm catching up, but don't worry, it will be updated ASAP."
Power savings. Trading upgradeability for unplugged battery life because publications put way too much emphasis on it for years trying to make arm seem better than x86.
I disagree. Battery life beyond a certain point is silly in a laptop, they aren't phones or tablets, which are much better suited for unplugged use for media consumption. Who the heck is spending 20 hours unplugged browsing the web? And at power performance than they would have if they were plugged in. I have supported thousands of laptops, lots of them macs, and any that do real work are plugged in.
Battery life used to be measured in minutes and was a big deal but now that we are measuring near days it's getting silly.
People work plugged in because they have to, not because they want to. as more powerful workload, capable all day and multi day, devices become available, they will be the choices for huge numbers of people who can afford the price.
Once all the players jump in, and there is more competition in price, extended battery life devices that can be worked on will dominate.
Maybe you want a battery that can still do a 8 hour workday 5 years after you bought it? Battery degradation is a thing you know.
I could throw your question right back at you. Why does anyone need upgradeability on a modern laptop? CPUs last a LONG time, by the time the CPU is no longer fast enough, the whole generation will be unsupported anyway, and the device a relic of the past. Just buy enough memory to do what you need and use the machine.
Disaster for Intel. Finally they folded. Intel fabs are now not even used for their high volume BGA junk processors. Instead using TSMC.
Second thing is as everyone pointed out they are comparing LP-E to E cores lol to inflate the graphs. Also the IPC is meager at best, Raptor Cove is faster than Meteor one and they are using that figure.
ARL will lack HT on top of this reduced clockrate, interesting times ahead for Desktop battle.
They aren’t comparing LP E-Cores to E-Cores. LNL E-cores are separated from the LLC, same as MTL island cores. It’s an apt comparison.
On the flip side, the comparison to Raptor cove is with E-cores connected to the LLC and ring bus, just as Raptor cove would be. It’s also an apt comparison. You’ll see island E-cores only on LNL (because of the power advantages) and ring bus connected E-cores on Arrow Lake (because of the performance advantages).
I don't know, but I am pretty underwhelmed. Intel is the least trusted tech giant, even Nvidia look better when it comes to honesty.
Here it seems like Intel took two steps forward, and three steps back. They are probably at a loss in either pricing, efficiency, or performance. Or more likely all three. That's why they use smoke and mirrors and try to trick the viewers/shareholders with the technicalities.
It's not like AMD didn't do the same, but they stand behind their technology, and actually showcased real products. And they also gave benchmarks. That's how you know they are confident.
It seems the CPU and GPU space is going to be a bloodbath for Intel. And we need all the competition we can get. But it is a little amusing to seeing Intel squirm. Ironically Intel is going the way of Bulldozer (shared cores) whilst AMD is sticking with Hyperthreading (extra bits per core) design. It's only amusing because Intel did unethical and illegal business practices that led to AMDs bankruptcy more than a decade ago. Microsoft is also complicit in that.
Sounds like an intel employee. People care about performance, not excuses, the problem with the comparison is that the LP-E cores are much inferior to the already deficient E-Cores.
Not sure if this was a reply to me because of page breaks, but if it was, what about what I said is untrue or biased?
From the (excellent, by the way) Chips article: "I wonder if Intel could give low power Crestmont a larger L2 cache, or even drop some blocks on Meteor Lake’s SoC tile to make room for a system level cache." - this is exactly what was done in Lunar Lake. The LNL E-Cores don't access the same L3 as the P-Cores, but there's an 8MB System level cache that they can access (that the rest of the chip also can I think, P-Cores, GPU, and NPU included). That probably is a big part of the giant 40-70% performance gain they show.
And E-Cores connected to the ring bus ARE much better, by Intel's own admission and by, again, the Chips article. Skymont E-Cores coming to ARL are (presumably) on the ring bus, and should punch much better than LNL E-Cores because of it.
None of this means that Intel's design is the best, or that it's not going to fall flat. That devil is still in the details, which Intel still needs to give to us. But I'm not sure how we can argue that the explicit details of the implementation are somehow biased or an excuse. That IS how Intel designed the chip; whether or not it is a good design remains to be seen. IMO, it seems like a pretty decent concept, but we'll have to see how much power the new P-Cores are really saving. With a 4P+4e design, they will need to be pretty efficient to match what Zen 5 will be up to, even in low power setups. (I assume 15W and above will get an arrow lake design that has more p cores and/or E cores on the ring bus).
One other thought - based on the Chips and Cheese article, LP E-Cores seem to be anywhere from 10-30% slower without access to an L3 cache. That Intel is calling out a 40-70% gain in Skymont LPE core performance over Crestmont LP-E is pretty noteworthy if nothing else. Even at their 10% (which is nuts) margin of error, the LPE core Skymont cores (albeit at least with access to a system cache) are as fast as Crestmont cores with a full blown 24MB L3 cache.
Again, benchmarks are king, but assuming Skymont LP-E is bad because Crestmont LP-E was bad seems like a poor assumption given the underlying conditions are completely different.
On the P side, most interesting is Lion Cove's moving to a split-scheduler design, saying good-bye to their classic unified approach there since the P6. AMD, always thinking ahead, has been using the split scheduler since the Athlon.
With confirmation that the entire compute tile is made on TSMC's N3B process, I guess we can take that to mean Intel was not super confident in mass yields on its own 20A process. Intel's 20A will be used in Arrow Lake, the desktop equivalent to Lunar Lake. Desktop shipments are a small fraction of laptop chips nowadays, so that makes sense. This does create a really interesting opportunity that I hope Anandtech will explore, where you could take a desktop Arrow Lake processor, disable enough P-cores and E-cores to make it equal to Lunar Lake, and see how they compare. Same architectures, but one on TSMC N3B versus Intel 20A.
20A is best thought of as an internal only, early sampling of 18A for use on the Compute Tile.
But LNL differs from ARL in that its compute tile also contains the iGPU and NPU, making 20A not an appropriate choice. 18A would've been the node Intel would've needed, but that's not until next year (coincidently, LNL's direct successor, PNL, will use 18A for it's unified compute tile instead of TSMC)
Or we could take it to mean that intel reserved a lot of N3B capacity and so figured they might as well use it. Like Apple, they will probably be looking to get off of N3B ASAP. While Apple moves to N3E, Intel will leap ahead to A18.
"This uplift is noticed, especially in the betterment of its hyper-threading, whereby improved IPC by 30%, dynamic power efficiency improved by 20%, and previous technologies, in balancing, without increasing the core area, in a commitment of Intel to better performance, within existing physical constraints."
So hyper threading is bother present and improved, yet they disabled it? This seems non sensical
I'm not asking why they disabled HT, we've known they were going to disable HT for some time. Disabling HT out of the box doesn't do anything because we've always been able to disable HT ourselves. I'm asking why they improved it if they are going to disable it, why waste a bunch of transistors and die area on a disabled feature? And if maybe the decision came too late to be removed, why brag about a thing that isn't even enabled?
Unfortunately, this feels like word salad from Anandtech. I won’t speculate how or why it was left in, or why Anandtech is quoting a 30% gain in IPC that is nowhere in Intel’s slides or on other tech website coverage.
They didn’t improve hyperthreading and then disable it. They removed the feature completely, and netted the die area and power savings from doing so. They probably also took a MT loss, but the die area and power savings could have been redirected to either better usage of the area for more performance, or just direct cost and efficiency savings. Intel’s hyperthreading was always a really inefficient way to gain a small amount of performance anyways. The actual side, published on Techpowerup’s dive, says removing hyperthreading saved them 5% perf/power, 15% perf/area, and 15% perf/power/area. That slide doesn’t appear to be published on Anandtech.
Essentially, they didn’t waste a bunch of transistors on a disabled feature - they did the obvious thing and physically removed the feature from the die. The description here is Anandtech’s fault, not Intel’s.
Thank you for your reply and the suggestion to check the techpowerup article. I would expect you are correct like the techpowerup article that HT was removed from the design and silicon, but I've also just read the pcworld lunar lake article which seems to suggest otherwise and amazingly has a slide not found in the techpowerup or anandtech articles.
What I think might be going on is that lion cove still has HT in the design because Intel wants it for server chips, although I'd argue it's not necessary there either and by the looks of their recent all E core xeons the thread count sensitive clients should be running those anyways. That would explain why they might improve HT. If that is the case is there 2 lion cove designs, one with HT and another without? I just read the wccftech article which suggests this is the case, mentioning "variants" of lion cove.
Since this lion cove core for lunar lake is being made at tsmc, it makes sense they had to make a new design for their fab anyways so maybe they did remove HT, and wccftech says they removed TSX and AMX also. So the lion cove for Intel fab coming to arrow lake/xeon might have HT, will definitely have TSX and AMX, but they might still turn HT off and only enable for xeon.
Regardless yeah the anandtech mention of HT improvements here in relation to lunar lake seems off base. But I still think there is more Intel could clear up on HT status on die and whether there are multiple lion cove designs.
I think they (techpowerup and pcworld) are both right. Per Tomshardware, commenting on Intel removing HT:
"As such, Intel architected two versions of the Lion Cove core, one with and one without hyperthreading, so that the threaded Lion Cove core can be used in other applications, like we see in the forthcoming Xeon 6 processors."
I expect the LNL physical design lacks HT, as that's the only way to actually get the performance/area and performance/watt savings. But we'll probably see the version of Lion Cove with hyper threading show up in the Xeon world (although, to be honest, I'm not sure if it's worth it there given the efficiency losses), as well as on Arrow Lake, where higher performance in exchange for an efficiency loss tends to be an acceptable tradeoff for PC Enthusiasts.
The Tomshardware article also points out to me where Anandtech's article summary gets the 30% number: "Intel’s architects concluded that hyperthreading, which boosts IPC by ~30% in heavily threaded workloads, isn’t as relevant in a hybrid design that leverages the more power- and area-efficient E-cores for threaded workloads." - this is coupled with yet another slide that shows Intel quoting hyperthreading as a +30% throughput for +20% Cdyn.
In other words, I think *lunar lake* does not feature hyperthreading - it's physically non-present in the design. Lion Cove the P-Core microarchitecture, on the other hand, has two designs - one with HT physically present (in Arrow Lake and any Xeon SKUs - speculation), and one without (in Lunar Lake only).
On that note, it also implies two different Modules for e-core as well - one with the e-cores not present on the ring bus (in Lunar Lake) and one where it's connected to the ring bus like "normal" - this being the config in Alder Lake and Raptor Lake (and this is presumably coming in Arrow Lake higher power laptop SKUs and the desktop)
Thank you for indulging me in this detailed discussion. I think you are right there are 2 lion cove designs. I don't think all the news outlets are aware of it.
There will be Lion Cove with hyperthreading. It is designed such that it can be physically left out or included in depending on the value to each product.
It was left out of Lunar Lake as the primary goal here is performance per watt and battery life superiority over Apple and Qualcomm.
Server Lion Cove will absolutely have hyperthreading. Rumors are Arrow Lake will have it as well.
So would this have on package memory, what is the size of memory? how many P cores how many E cores? So many questions no answers. Is this like a paper launch?
I wonder if the tag RAM for the L0, L1D, and L2 are all separate? It would be interesting if they grouped it all together in a tree-structured lookup and put that as close as possible to the core's load/store unit. The actual data memory of the caches could be the only part that's physically separate.
It's worth the wait to Lunar and Arrow? Or take advantage of the Intel and AMD current generation clearance sales?
Intel is flooding the channel with Raptor desktop and mobile in the last eight weeks apparently to sustain a Core supply bridge' into Lunar and Arrow. Intel is also sucking the financial capital out of the channel in an effort to block or slow the procurement of anything other than Intel.
In parallel fighting it out for surplus control, AMD is also engaged sucking financial capital out of the channel by flooding the channel specifically with Raphael desktop.
Where Meteor Lake and AMD Phoenix, Hawks and Granite Ridge continue as intermediate 'Al' technologies into Strix mobile and Arrow desktop. Not that I care about AI functionality currently.
14th desktop channel available + 98% in the prior eight weeks 13th desktop + 24.6% 12th desktop + 33.4%
Intel desktop all up;
14th desktop available today = 24.9% 13th desktop = 37% that is 48.4% more than 14th 12th desktop = 37.9% equivalent with 13th
Specific Intel mobile;
Intel Meteor Lake mobile channel available gains + 216%. Within Meteor Lake Core SKUs are 10.3%. Among total, H performance mobile = 43.9% and U low power mobile = 56%. Meteor Lake associated are 11% of all Raptor Lake 13th mobile.
14th mobile H + 16% in week and 30% of all Meteor and 36% of all 13th Raptor mobile H. 13th mobile itself gains + 5.1% 13th H specifically gains + 8.6% 13th P clears down < 3.2% 13th U gains + 4.8%
12th Alder mobile all up + 13.2% in the prior eight weeks 12th H specifically = flat 12th P clears down < 3.2% 12th U clears down < 2.6%
I will have AMD desktop and mobile supply, trade-in and sales trend up later today at my SA comment line. Here are some immediate observations;
5900XT and 5800XT on AMD so said pricing is sufficient to push Vermeer channel holdings down in price at so said $359 and $249 now pulled by AMD in the moment. The channel might not have been happy with that regulating price move on how much R5K there is too clear from the channel. R5K channel available is up + 68% since March 9 when R5K was 68% of all R7K and today 98% of R7K available.
R7K desktop since March 9 channel supply volume available + 18%. R9K will minimally dribble out allowing R7K and R5K to clear? R9K might have to be priced up on specific SKUs to accomplish the same dribbling out objective allowing AMD back generation to clear?
Notably 3600 gains in the channel + 94% in the prior month. 3600X came back to secondary resale + 35%. 3700X is up + 15.8% that's all trade-in.
AMD might have to adjust R9K desktop top SKU and R5K desktop regulating SKUs not to interfere with the channel's ability to liquidate especially Vermeer from channel inventory holdings plus R7K SKUs that will follow in a first in first out channel sales system.
In summary, there is plenty of Intel and AMD product in the channel. The PC market remains in a downward deflationary price spiral until at least q1 2025 aimed to clear existing inventories for channel financial reclaim to buy next generation.
Subsequently there's this inventory bridge to traverse to Intel and AMD next generation products and through the summer into q4 it's never been a better time to buy a PC. I don't think desktop and mobile prices will be as low as they are heading into year end and for a long time following.
For Intel at least flooding the channel with product indicates Intel is buying time.
Thanks BushLin, I also find all the engineering and end use perspectives interesting as a compliment resource specific market observations I triangulate for common perspective and some not so common perspectives from time to time.
My full AMD workstation, desktop and mobile what's selling in the last 6 weeks report is now posted at Seeking Alpha.
I posted here in comment string and just look down comments to the pointer and the full report is easily downloadable. There is also a pointer within the downloadable report itself to the same Intel data last eight weeks.
In answer to your question, "It's worth the wait to Lunar and Arrow?"
In terms of Intel's CPU/GPU performance, I doubt it.
In terms of power efficiency, they might have caught up. We'll have to wait for reviews. Only partially refreshing the screen should lead to a nice performance improvement and/or efficiency improvement of the GPU.
In terms of QoL improvements, it looks like Intel went all out for this new generation. In the following statements, I'm assuming that Intel's able to deliver. Having multiple TB4 ports is useful. Having TB4 with the ability to transfer files is also useful. So is better Wi-Fi. If anything, this might be *the* killer feature of the series. Likewise, VVC, assuming it's not badly licenced, should prove useful. I wonder if VVC is supported by their Quicksync encoder...
Don't misunderstand me, I appreciate what you've said above. But I really don't see this gen failing badly unless AMD/Qualcomm can equal them in terms of useful features.
I also think Intel's on it way back to mobile efficiency. While Meteor is ramping, I perceive OEMs from channel data and enterprise IT especially Intel shops on 'applications utility' value, and validation, waiting for Lunar / Arrow and or Strix. Granite Ridge I see facing an AM5 saturation issue and there is sooo much Raphael and Vermeer in the channel to clear R9K price will likely be held up while Raptor/Alder and Raphael/Vermeer nose dive on channel liquidation for capital reclaim to buy new like q4 into first half 2025.
From the channel data AMD and Intel are dumping all over Snapdragon X whose launch is into a deflationary price cycle at least through q1 2025. Lots of downward price and margin pressure.
Me, I am looking for a new (used) laptop, more a desktop replacement than Office low power and AI does not matter to me currently. I was interested in a used Tiger Octa or Cezanne H_ with MXM GPU but waiting a wee bit more because laptop prices including gaming are in a nose dive. Means I'll be able to move up to new 13th Raptor in overage supply condition or used Alder or Rembrandt H with minimally Ampere. AMD Cezanne and Rembrandt and 13th and 12th pricing just let go and it get's better into q4. See my Seeking Alpha report on supply, trade-in and sales trend pointed to above.
Though my computer is all right, I'd like to upgrade to Cezanne or Renoir, either 5600G or 4600G. (It will likely be the latter because of motherboard woes.) Here, the prices have been stuck for ages. Do you think they'll ever drop?
GeoffreyA, I'm not involved with the markets like Mr. Bruzzone, but my recent experience with trying to get a GPU for 4 years in a row says, "Yes, prices will go back down."
5600G and 4600G are weird parts because they're dependent on AMD's mobile positioning. The latter (4600G) isn't being manufactured anymore to my knowledge -- Renoir is useless now to AMD because it was supplanted in mobile by the updated Mendocino platform, which likely will never be brought to desktop. I am not sure pricing on the 4600G will ever make sense.
5600G is Cezanne, which is still being manufactured for 7x30 series (or was until recently).
However, at this point Cezanne is 7nm and easily binned, but there is no direct 5600G replacement yet as AMD did not launch a 7000 series G product. The 8000G series (just announced) should push 5600G into clearance pricing.
Thanks. Good explanation. I'd go for the 5600G, but my motherboard, B450 Tomahawk, apparently has issues with this very CPU, despite there being BIOS support for quite some time. Online, people haven't had a solution, and MSI says nothing.
Hey, where's the rest of the slide deck? There are definitely some slides I've seen elsewhere that aren't featured in the article. I'm used to this site posting the entire slides at the end.
so lunar lake soc die proves that Intel fake 4 is worse than tsmc n6
and if the soc / platform controller is included in the compute die, it won't need tsv. the lunar lake will be much simpler, perform better and might be cheaper
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thestryker - Monday, June 3, 2024 - link
I'm curious what the overall E-core performance is going to look like since the cluster won't have L3 cache access. Chips and Cheese did some analysis of the LP E-cores on MTL and found this specifically to be a big negative. I'm guessing this design is going to be limited to just LNL and is predominantly for the power savings.ET - Tuesday, June 4, 2024 - link
Interestingly, Intel is comparing Skymont to Raptor Cover. I agree that we have to wonder how the L3 (or lack thereof) affect this, but from the Chips and Cheese figures alongside Intel's performance improvement figures, it looks like Skymont without L3 cache will be faster than Crestmont with L3 cache.kwohlt - Tuesday, June 4, 2024 - link
There's 8MB of "SOC cache", separate from both the P and E cores, that should in practice function as the E cores' L3thestryker - Tuesday, June 4, 2024 - link
That's my assumption as well as I think the GPU would be the other part predominantly using it and they shouldn't really both be hitting it at the same time.sharath.naik - Monday, June 10, 2024 - link
Side cache is not the same as L3, or I think they would have called it that. shared L3 is where the memory sync can happen across cores. if not, it needs to go all the way back to ram. So, side caches really cannot be considered as L3, more like expanded L2 for E-core and expanded l3 for P-Core? is my guess. Yes, it means things that run on both E-Core and P-Core, at the same time, will take a hit on performance. I think they were targeting the majority use case. where most won't need more than 4 threads or threads won't be working on the same data.powerarmour - Thursday, June 6, 2024 - link
I can see this being an embarrassing launch if it gets slapped around by Qualcomm's SDx Elitemode_13h - Friday, June 7, 2024 - link
Well, they're on a better node that Qualcomm, so there's that.sharath.naik - Monday, June 10, 2024 - link
It absolutely will. Because this is going to be slower than meteor lake in CPU. Elite is supposed to be 30% faster. Intel should have released 8 P-core version to compete in performance. But I think they wanted to reserve that to be produced on their own fabs.lmcd - Monday, June 17, 2024 - link
Snap Elite is supposed to be 30% faster at essentially-undisclosed power. Lunar Lake will ironically undercut the Snapdragon Elite on power and cost while delivering good performance.Drumsticks - Tuesday, June 4, 2024 - link
I hate to ask this, but was this article fully written by Gavin and proof'ed by another editor? Was there a deadline push to get it out as soon as Intel released the information on Lunar Lake? It just reads so, so disjointed. It feels like there are so many issues in this paragraph alone on the P-core overview; it feels jarring to read."This Lion Cove architecture **also aligns with performance increases**, boasting a predicted double-digit bump in IPC over the older Redwood Cove generation. This uplift is noticed, especially **in the betterment of its hyper-threading, whereby improved IPC** by 30%, dynamic power efficiency improved by 20%, **and previous technologies, in balancing**, without increasing the core area, **in a commitment of Intel to better performance**, within existing physical constraints."
I've seen so much better work from Gavin, and Anandtech in general, that I almost hope that this page was heavily written by software. I know it's a press release, and there's not a whole lot of information, but the level of first party detail here feels similar to the Architecture Day 2021 presentations Intel did on Alder Lake, which got fantastic coverage from Andrei and Dr. Cuttress, and here it feels like we are getting a poorly worded restating of the slides with hardly any analysis or greater than surface level understanding.
I've been reading Anandtech since I was 15, and the level of detail in the Sandy Bridge era articles honestly had a huge influence on my choice to pursue a career in CPU Design. I've mountains of respect for what Anandtech has published in the past, but this article feels rushed.
Ryan Smith - Tuesday, June 4, 2024 - link
"Was there a deadline push to get it out as soon as Intel released the information on Lunar Lake?"Yes. There was a hard deadline on this. Copyediting is ongoing.
Drumsticks - Tuesday, June 4, 2024 - link
Thank you for responding. I hope there’s an opportunity to address some of the writing at a bare minimum and maybe inject some of your own voice.Lunar Lake honestly looks like a pretty big deal. The process is great, the microarchs seem impressive on paper, and it’s coming out to market within a quarter of when it needs to, not within three years. Looking forward to deeper analysis and comparisons, wherever they come from, when the time comes.
NetMage - Tuesday, June 4, 2024 - link
A deadline for what? To regurgitate Intel PR hype as an LLM enhanced unreadable English as a second language article before everyone else publishes their copy of Intel’s Press Release? This article should have never been published.The Xe2 page is particularly horrendous.
Terry_Craig - Thursday, June 6, 2024 - link
There's nothing particularly interesting about Lunar Lake that deserves all this hunger for high-quality content.mode_13h - Friday, June 7, 2024 - link
Sarcasm detected.eastcoast_pete - Tuesday, June 4, 2024 - link
Now, I also like good copy editing, but this kind of coverage is done almost in real time. That, plus the time zone difference makes it hard to have a fully copy-edited and proofed article posted, all within hours of the presentation.Drumsticks - Wednesday, June 5, 2024 - link
I understand that. Anandtech has done it in the past, and produced really stellar coverage that way. I'm a little surprised that some of the paragraphs haven't gotten complete, proper rewrites more than 36 hours after the article went live. (To be fair, that's one business day really). But it's a headliner article on their front page; I'd hoped for more love.skavi - Tuesday, June 4, 2024 - link
Thank you for writing this out. Similar feelings, but I could not have put it so well. Here’s hoping AnandTech can figure out how to get back to that level of quality.Strom- - Tuesday, June 4, 2024 - link
I loved reading about the benefits of Thunderbolt 5.EthiaW - Tuesday, June 4, 2024 - link
Well done Intel, receiving enormous CHIPS subsidy while hollowing out production to TSMC tile by tile.mode_13h - Tuesday, June 4, 2024 - link
Yeah, it definitely comes across as two-faced for Intel to be pitching its foundry business to others, while it's not even using it for its own cutting-edge CPUs!kn00tcn - Tuesday, June 4, 2024 - link
1) bob (or brian?) made a deal with tsmc and they need fill the required capacity2) tsmc chiplet packaging requires all tiles to come from tsmc (but mixing tile foundries is fine as long as someone else packages)
3) lunar lake isnt high power high core desktop/server, there's plenty else to make themselves, and obviously they've been ramping cutting edge future nodes
4) these things take years, why would a recent subsidy relate to old deals
mode_13h - Thursday, June 6, 2024 - link
> 1) bob (or brian?) made a deal with tsmc and they need fill the required capacityThis is probably the dumbest claim I've seen in a while. There's guaranteed to be an escape clause in that contract, although Intel would be stuck with some fee.
Given the current demand for cutting-edge nodes, I'm sure Intel could probably work out an agreement with another fab customer to buy their excess wafer capacity and probably even turn a profit by it.
> 2) tsmc chiplet packaging requires all tiles to come from tsmc
Second dumbest claim in the thread. Lunar Lake uses Foveros, not TSMC's technology, and Intel is making the base layer on their own 22 nm node.
> 3) lunar lake isnt high power high core desktop/server
What does that have to do with anything? It still needs to compete on performance and efficiency!
> why would a recent subsidy relate to old deals
Who said anything about that?
kwohlt - Tuesday, June 4, 2024 - link
Intel's foundry service doesn't have a full suite of nodes to choose from and is currently building out a fabs. In the meantime, client will be using some of the TSMC N3B allocation that Intel carved out years ago. Expect 2024-2025 to be peak TSMC usage.What other options were realistically available? Intel 3 is just hitting the market and fully allocated to Xeon 6 initially. Intel 4 isn't library complete and wouldn't work for a tile that also contains NPU and GPU. Intel 7 is heavy DTCO'd for ADL/RPL and has poor low wattage performance. 18A isn't ready yet.
By the time 14A releases, Intel will have a selection of 18A and the Intel 3 family of nodes to pick from for their other CPU tiles.
mode_13h - Thursday, June 6, 2024 - link
> Intel 3 is just hitting the market and fully allocated to Xeon 6 initiallyThe Lunar Lake CPU tiles can't be very big. They should've been a good "pipe cleaner" product for Intel to ramp up their "3" node, before making the huge Xeon dies.
I hadn't noticed the GPU was on the same tile. If true, I think they could've kept it on its own tile, as Meteor Lake did.
lmcd - Wednesday, June 12, 2024 - link
Intel has not shipped an Xe product on an Intel process since DG1. We don't know that it ports.Adding a separate die might have increased the package size, and part of the point of this product was to be a small package that could supplant Qualcomm designs easily (and the PMIC callout was specifically targeted at vendors that got burned by Qualcomm's power shenanigans, if you believe Charlie).
andrewaggb - Thursday, June 6, 2024 - link
yeah, it's not a great look on the fab side, but honestly I hope it's an amazing chip and worth upgrading. I hope Qualcomm's chip is great as well and get some actual innovation/competition going on.eonsim - Tuesday, June 4, 2024 - link
Is Intel comparing there new E-cores to the LP-E cores here (the ones on the SoC with no L3), rather than the main E-cores for Meteor lake?mode_13h - Tuesday, June 4, 2024 - link
+1name99 - Wednesday, June 5, 2024 - link
Exactly.And judging from what I've seen on the internet, plenty of people were fooled. And don't like to be told that they were fooled...
mode_13h - Thursday, June 6, 2024 - link
The way I see it, the only defense Intel has for comparing Skymont to the LP Crestmont cores is to defend their decision not to include a separate LP version of Skymont, in Lunar Lake.In fact, I'll bet what happened is that someone internally made this pitch and the marketing goon who produced the public-facing slides for Lunar Lake opted to reuse that data, since it made Skymont look even better (it's already quite impressive)!
kwohlt - Tuesday, June 4, 2024 - link
The MTL E cores shared a ringbus with the P cores. The LNL E cores are completely separated from the P cores and function much more similarly to current LP-E coresname99 - Wednesday, June 5, 2024 - link
So how much faster are they than the MTL E-cores (as opposed to the LP-E cores)?Sure it's nice that the dumbness of MTL is fixed, but the question is the one I'm interested in.
mode_13h - Tuesday, June 4, 2024 - link
So is L0D just a new name for what they previously called L1D? The two seem virtually identical, at least in terms of the information they disclosed.mode_13h - Tuesday, June 4, 2024 - link
The thing they're *now* calling L1D is what seems to be the new part.Dante Verizon - Tuesday, June 4, 2024 - link
AMD will be swimming ahead, how pathetic.lmcd - Monday, June 17, 2024 - link
AMD doesn't build a package that competes with this product. If Intel delivers with Xe2 (and there's no reason to believe they will, to be clear), this product would win the entire handheld gaming category for the generation in about 30 seconds flat. Lunar Lake wouldn't actually be impossible to stuff into a phablet-style phone, though it obviously wouldn't be easy.kkilobyte - Tuesday, June 4, 2024 - link
what about the i9-14900KS test redo with Intel Default settings? You told us 20 days ago that you'd redo them :Gavin Bonshor - Friday, May 10, 2024 - link
Don't worry; I will be testing Intel Default settings, too. I'm testing over the weekend and adding them in.
So, will this promise be ever fullfilled?
kn00tcn - Tuesday, June 4, 2024 - link
are you confirming that he chart images have not changed or were you waiting for an announcement?kkilobyte - Tuesday, June 4, 2024 - link
Unless I'm mistaken, the charts don't seem to have changed, and include only a single set of data (without the Intel Default Settings). The text doesn't suggest they were, though I didn't read the whole article again, I admit.BushLin - Wednesday, June 5, 2024 - link
Seconded, also..."Gavin Bonshor - Tuesday, May 21, 2024 - link
Hey, thank you for saying that. They are coming as soon as I can get the data updated. I had to fly out to the USA last Monday evening, and the testing wasn't finished in time. I also don't typically work weekends, but I made an exception in this case. I'm catching up, but don't worry, it will be updated ASAP."
TheinsanegamerN - Monday, June 10, 2024 - link
Nope. We never got that Macbook review or the return of the GPU benchmarks.jaj18 - Tuesday, June 4, 2024 - link
What's the improvement from on package memory🤔?rgreen1983 - Tuesday, June 4, 2024 - link
Power savings. Trading upgradeability for unplugged battery life because publications put way too much emphasis on it for years trying to make arm seem better than x86.The Hardcard - Wednesday, June 5, 2024 - link
There’s not way to emphasis on it. Battery life is a far more mainstream issue than upgradability.rgreen1983 - Wednesday, June 5, 2024 - link
I disagree. Battery life beyond a certain point is silly in a laptop, they aren't phones or tablets, which are much better suited for unplugged use for media consumption. Who the heck is spending 20 hours unplugged browsing the web? And at power performance than they would have if they were plugged in. I have supported thousands of laptops, lots of them macs, and any that do real work are plugged in.Battery life used to be measured in minutes and was a big deal but now that we are measuring near days it's getting silly.
The Hardcard - Thursday, June 6, 2024 - link
People work plugged in because they have to, not because they want to. as more powerful workload, capable all day and multi day, devices become available, they will be the choices for huge numbers of people who can afford the price.Once all the players jump in, and there is more competition in price, extended battery life devices that can be worked on will dominate.
TheinsanegamerN - Monday, June 10, 2024 - link
Maybe you want a battery that can still do a 8 hour workday 5 years after you bought it? Battery degradation is a thing you know.I could throw your question right back at you. Why does anyone need upgradeability on a modern laptop? CPUs last a LONG time, by the time the CPU is no longer fast enough, the whole generation will be unsupported anyway, and the device a relic of the past. Just buy enough memory to do what you need and use the machine.
See how easy that is?
shabby - Tuesday, June 4, 2024 - link
Thanks tsmc for saving Intel's butt, they couldn't do it themselves with 10nm+++++++Nate_on_HW - Tuesday, June 4, 2024 - link
I found it interesting that they also talked about the INT8 OPS throughput of the GPU and CPUWould find it interesting to get those numbers on AMDs &Qualcomms chip and maybe plot each module of the SoCs as "TOPS/Watt" (for comparison)
I wonder if the new windows11 "on-device ML-models" would use the whole chip for computing or only the NPU.
Silver5urfer - Tuesday, June 4, 2024 - link
Disaster for Intel. Finally they folded. Intel fabs are now not even used for their high volume BGA junk processors. Instead using TSMC.Second thing is as everyone pointed out they are comparing LP-E to E cores lol to inflate the graphs. Also the IPC is meager at best, Raptor Cove is faster than Meteor one and they are using that figure.
ARL will lack HT on top of this reduced clockrate, interesting times ahead for Desktop battle.
Drumsticks - Tuesday, June 4, 2024 - link
They aren’t comparing LP E-Cores to E-Cores. LNL E-cores are separated from the LLC, same as MTL island cores. It’s an apt comparison.On the flip side, the comparison to Raptor cove is with E-cores connected to the LLC and ring bus, just as Raptor cove would be. It’s also an apt comparison. You’ll see island E-cores only on LNL (because of the power advantages) and ring bus connected E-cores on Arrow Lake (because of the performance advantages).
Kangal - Wednesday, June 5, 2024 - link
I don't know, but I am pretty underwhelmed.Intel is the least trusted tech giant, even Nvidia look better when it comes to honesty.
Here it seems like Intel took two steps forward, and three steps back. They are probably at a loss in either pricing, efficiency, or performance. Or more likely all three. That's why they use smoke and mirrors and try to trick the viewers/shareholders with the technicalities.
It's not like AMD didn't do the same, but they stand behind their technology, and actually showcased real products. And they also gave benchmarks. That's how you know they are confident.
It seems the CPU and GPU space is going to be a bloodbath for Intel. And we need all the competition we can get. But it is a little amusing to seeing Intel squirm. Ironically Intel is going the way of Bulldozer (shared cores) whilst AMD is sticking with Hyperthreading (extra bits per core) design. It's only amusing because Intel did unethical and illegal business practices that led to AMDs bankruptcy more than a decade ago. Microsoft is also complicit in that.
Terry_Craig - Wednesday, June 5, 2024 - link
Sounds like an intel employee. People care about performance, not excuses, the problem with the comparison is that the LP-E cores are much inferior to the already deficient E-Cores.https://chipsandcheese.com/2024/05/20/comparing-cr...
Drumsticks - Tuesday, June 11, 2024 - link
Not sure if this was a reply to me because of page breaks, but if it was, what about what I said is untrue or biased?From the (excellent, by the way) Chips article: "I wonder if Intel could give low power Crestmont a larger L2 cache, or even drop some blocks on Meteor Lake’s SoC tile to make room for a system level cache." - this is exactly what was done in Lunar Lake. The LNL E-Cores don't access the same L3 as the P-Cores, but there's an 8MB System level cache that they can access (that the rest of the chip also can I think, P-Cores, GPU, and NPU included). That probably is a big part of the giant 40-70% performance gain they show.
And E-Cores connected to the ring bus ARE much better, by Intel's own admission and by, again, the Chips article. Skymont E-Cores coming to ARL are (presumably) on the ring bus, and should punch much better than LNL E-Cores because of it.
None of this means that Intel's design is the best, or that it's not going to fall flat. That devil is still in the details, which Intel still needs to give to us. But I'm not sure how we can argue that the explicit details of the implementation are somehow biased or an excuse. That IS how Intel designed the chip; whether or not it is a good design remains to be seen. IMO, it seems like a pretty decent concept, but we'll have to see how much power the new P-Cores are really saving. With a 4P+4e design, they will need to be pretty efficient to match what Zen 5 will be up to, even in low power setups. (I assume 15W and above will get an arrow lake design that has more p cores and/or E cores on the ring bus).
Drumsticks - Tuesday, June 11, 2024 - link
One other thought - based on the Chips and Cheese article, LP E-Cores seem to be anywhere from 10-30% slower without access to an L3 cache. That Intel is calling out a 40-70% gain in Skymont LPE core performance over Crestmont LP-E is pretty noteworthy if nothing else. Even at their 10% (which is nuts) margin of error, the LPE core Skymont cores (albeit at least with access to a system cache) are as fast as Crestmont cores with a full blown 24MB L3 cache.Again, benchmarks are king, but assuming Skymont LP-E is bad because Crestmont LP-E was bad seems like a poor assumption given the underlying conditions are completely different.
GeoffreyA - Tuesday, June 4, 2024 - link
On the P side, most interesting is Lion Cove's moving to a split-scheduler design, saying good-bye to their classic unified approach there since the P6. AMD, always thinking ahead, has been using the split scheduler since the Athlon.Blastdoor - Tuesday, June 4, 2024 - link
This really looks like a SOC made for a MacBook Air.lmcd - Wednesday, June 12, 2024 - link
Or intended to beat out Snapdragon Elite if its date didn't slip.NextGen_Gamer - Tuesday, June 4, 2024 - link
With confirmation that the entire compute tile is made on TSMC's N3B process, I guess we can take that to mean Intel was not super confident in mass yields on its own 20A process. Intel's 20A will be used in Arrow Lake, the desktop equivalent to Lunar Lake. Desktop shipments are a small fraction of laptop chips nowadays, so that makes sense. This does create a really interesting opportunity that I hope Anandtech will explore, where you could take a desktop Arrow Lake processor, disable enough P-cores and E-cores to make it equal to Lunar Lake, and see how they compare. Same architectures, but one on TSMC N3B versus Intel 20A.kwohlt - Tuesday, June 4, 2024 - link
20A is best thought of as an internal only, early sampling of 18A for use on the Compute Tile.But LNL differs from ARL in that its compute tile also contains the iGPU and NPU, making 20A not an appropriate choice. 18A would've been the node Intel would've needed, but that's not until next year (coincidently, LNL's direct successor, PNL, will use 18A for it's unified compute tile instead of TSMC)
Blastdoor - Wednesday, June 5, 2024 - link
Or we could take it to mean that intel reserved a lot of N3B capacity and so figured they might as well use it. Like Apple, they will probably be looking to get off of N3B ASAP. While Apple moves to N3E, Intel will leap ahead to A18.The Hardcard - Wednesday, June 5, 2024 - link
Barring newly announced delays, TSMC will hit volume on N2 in the same timeframe as volume on Intel A18. Apple’s move to N3E has happened. N2 in 2025.rgreen1983 - Tuesday, June 4, 2024 - link
"This uplift is noticed, especially in the betterment of its hyper-threading, whereby improved IPC by 30%, dynamic power efficiency improved by 20%, and previous technologies, in balancing, without increasing the core area, in a commitment of Intel to better performance, within existing physical constraints."So hyper threading is bother present and improved, yet they disabled it? This seems non sensical
meacupla - Tuesday, June 4, 2024 - link
From what I have read and seen from other tech sites, Intel disabled HT because it wasn't working properly with E-cores.Disabling HT improves performance and efficiency, because the E-cores get utilized, instead of sitting idle on low power loads.
rgreen1983 - Tuesday, June 4, 2024 - link
I'm not asking why they disabled HT, we've known they were going to disable HT for some time. Disabling HT out of the box doesn't do anything because we've always been able to disable HT ourselves. I'm asking why they improved it if they are going to disable it, why waste a bunch of transistors and die area on a disabled feature? And if maybe the decision came too late to be removed, why brag about a thing that isn't even enabled?Drumsticks - Tuesday, June 4, 2024 - link
Unfortunately, this feels like word salad from Anandtech. I won’t speculate how or why it was left in, or why Anandtech is quoting a 30% gain in IPC that is nowhere in Intel’s slides or on other tech website coverage.They didn’t improve hyperthreading and then disable it. They removed the feature completely, and netted the die area and power savings from doing so. They probably also took a MT loss, but the die area and power savings could have been redirected to either better usage of the area for more performance, or just direct cost and efficiency savings. Intel’s hyperthreading was always a really inefficient way to gain a small amount of performance anyways. The actual side, published on Techpowerup’s dive, says removing hyperthreading saved them 5% perf/power, 15% perf/area, and 15% perf/power/area. That slide doesn’t appear to be published on Anandtech.
Essentially, they didn’t waste a bunch of transistors on a disabled feature - they did the obvious thing and physically removed the feature from the die. The description here is Anandtech’s fault, not Intel’s.
rgreen1983 - Tuesday, June 4, 2024 - link
Thank you for your reply and the suggestion to check the techpowerup article. I would expect you are correct like the techpowerup article that HT was removed from the design and silicon, but I've also just read the pcworld lunar lake article which seems to suggest otherwise and amazingly has a slide not found in the techpowerup or anandtech articles.What I think might be going on is that lion cove still has HT in the design because Intel wants it for server chips, although I'd argue it's not necessary there either and by the looks of their recent all E core xeons the thread count sensitive clients should be running those anyways. That would explain why they might improve HT. If that is the case is there 2 lion cove designs, one with HT and another without? I just read the wccftech article which suggests this is the case, mentioning "variants" of lion cove.
Since this lion cove core for lunar lake is being made at tsmc, it makes sense they had to make a new design for their fab anyways so maybe they did remove HT, and wccftech says they removed TSX and AMX also. So the lion cove for Intel fab coming to arrow lake/xeon might have HT, will definitely have TSX and AMX, but they might still turn HT off and only enable for xeon.
Regardless yeah the anandtech mention of HT improvements here in relation to lunar lake seems off base. But I still think there is more Intel could clear up on HT status on die and whether there are multiple lion cove designs.
Drumsticks - Tuesday, June 4, 2024 - link
I think they (techpowerup and pcworld) are both right. Per Tomshardware, commenting on Intel removing HT:"As such, Intel architected two versions of the Lion Cove core, one with and one without hyperthreading, so that the threaded Lion Cove core can be used in other applications, like we see in the forthcoming Xeon 6 processors."
I expect the LNL physical design lacks HT, as that's the only way to actually get the performance/area and performance/watt savings. But we'll probably see the version of Lion Cove with hyper threading show up in the Xeon world (although, to be honest, I'm not sure if it's worth it there given the efficiency losses), as well as on Arrow Lake, where higher performance in exchange for an efficiency loss tends to be an acceptable tradeoff for PC Enthusiasts.
The Tomshardware article also points out to me where Anandtech's article summary gets the 30% number: "Intel’s architects concluded that hyperthreading, which boosts IPC by ~30% in heavily threaded workloads, isn’t as relevant in a hybrid design that leverages the more power- and area-efficient E-cores for threaded workloads." - this is coupled with yet another slide that shows Intel quoting hyperthreading as a +30% throughput for +20% Cdyn.
In other words, I think *lunar lake* does not feature hyperthreading - it's physically non-present in the design. Lion Cove the P-Core microarchitecture, on the other hand, has two designs - one with HT physically present (in Arrow Lake and any Xeon SKUs - speculation), and one without (in Lunar Lake only).
On that note, it also implies two different Modules for e-core as well - one with the e-cores not present on the ring bus (in Lunar Lake) and one where it's connected to the ring bus like "normal"
- this being the config in Alder Lake and Raptor Lake (and this is presumably coming in Arrow Lake higher power laptop SKUs and the desktop)
rgreen1983 - Wednesday, June 5, 2024 - link
Thank you for indulging me in this detailed discussion. I think you are right there are 2 lion cove designs. I don't think all the news outlets are aware of it.The Hardcard - Wednesday, June 5, 2024 - link
There will be Lion Cove with hyperthreading. It is designed such that it can be physically left out or included in depending on the value to each product.It was left out of Lunar Lake as the primary goal here is performance per watt and battery life superiority over Apple and Qualcomm.
Server Lion Cove will absolutely have hyperthreading. Rumors are Arrow Lake will have it as well.
TMDDX - Wednesday, June 5, 2024 - link
Is on chip "AI" the new connected standby for NSA spying?ballsystemlord - Wednesday, June 5, 2024 - link
Shhhhh, you're not supposed to say that. It's classified. ;)sharath.naik - Wednesday, June 5, 2024 - link
So would this have on package memory, what is the size of memory? how many P cores how many E cores? So many questions no answers. Is this like a paper launch?sharath.naik - Wednesday, June 5, 2024 - link
Never mind I was wrong. 4E+4P and up to 32 GB RAM. I wish they had option for 64GB, but 32GB is a good numberstephenbrooks - Wednesday, June 5, 2024 - link
The wider Lion Cove core looks pretty impressive, I'll be interested to see how it does in desktops.name99 - Wednesday, June 5, 2024 - link
"In total, this puts 240KB of cache within 9 cycles' latency of the CPU cores"Does it? If they do things the usual Intel way the L1 is inclusive of the L0...
Other options are possible, of course, but were they implemented?
mode_13h - Thursday, June 6, 2024 - link
I wonder if the tag RAM for the L0, L1D, and L2 are all separate? It would be interesting if they grouped it all together in a tree-structured lookup and put that as close as possible to the core's load/store unit. The actual data memory of the caches could be the only part that's physically separate.Bruzzone - Wednesday, June 5, 2024 - link
It's worth the wait to Lunar and Arrow?Or take advantage of the Intel and AMD current generation clearance sales?
Intel is flooding the channel with Raptor desktop and mobile in the last eight weeks apparently to sustain a Core supply bridge' into Lunar and Arrow. Intel is also sucking the financial capital out of the channel in an effort to block or slow the procurement of anything other than Intel.
In parallel fighting it out for surplus control, AMD is also engaged sucking financial capital out of the channel by flooding the channel specifically with Raphael desktop.
Where Meteor Lake and AMD Phoenix, Hawks and Granite Ridge continue as intermediate 'Al' technologies into Strix mobile and Arrow desktop. Not that I care about AI functionality currently.
14th desktop channel available + 98% in the prior eight weeks
13th desktop + 24.6%
12th desktop + 33.4%
Intel desktop all up;
14th desktop available today = 24.9%
13th desktop = 37% that is 48.4% more than 14th
12th desktop = 37.9% equivalent with 13th
Specific Intel mobile;
Intel Meteor Lake mobile channel available gains + 216%. Within Meteor Lake Core SKUs are 10.3%. Among total, H performance mobile = 43.9% and U low power mobile = 56%. Meteor Lake associated are 11% of all Raptor Lake 13th mobile.
14th mobile H + 16% in week and 30% of all Meteor and 36% of all 13th Raptor mobile H.
13th mobile itself gains + 5.1%
13th H specifically gains + 8.6%
13th P clears down < 3.2%
13th U gains + 4.8%
12th Alder mobile all up + 13.2% in the prior eight weeks
12th H specifically = flat
12th P clears down < 3.2%
12th U clears down < 2.6%
I will have AMD desktop and mobile supply, trade-in and sales trend up later today at my SA comment line. Here are some immediate observations;
5900XT and 5800XT on AMD so said pricing is sufficient to push Vermeer channel holdings down in price at so said $359 and $249 now pulled by AMD in the moment. The channel might not have been happy with that regulating price move on how much R5K there is too clear from the channel. R5K channel available is up + 68% since March 9 when R5K was 68% of all R7K and today 98% of R7K available.
R7K desktop since March 9 channel supply volume available + 18%. R9K will minimally dribble out allowing R7K and R5K to clear? R9K might have to be priced up on specific SKUs to accomplish the same dribbling out objective allowing AMD back generation to clear?
Notably 3600 gains in the channel + 94% in the prior month.
3600X came back to secondary resale + 35%.
3700X is up + 15.8% that's all trade-in.
AMD might have to adjust R9K desktop top SKU and R5K desktop regulating SKUs not to interfere with the channel's ability to liquidate especially Vermeer from channel inventory holdings plus R7K SKUs that will follow in a first in first out channel sales system.
In summary, there is plenty of Intel and AMD product in the channel. The PC market remains in a downward deflationary price spiral until at least q1 2025 aimed to clear existing inventories for channel financial reclaim to buy next generation.
Subsequently there's this inventory bridge to traverse to Intel and AMD next generation products and through the summer into q4 it's never been a better time to buy a PC. I don't think desktop and mobile prices will be as low as they are heading into year end and for a long time following.
For Intel at least flooding the channel with product indicates Intel is buying time.
mb
BushLin - Wednesday, June 5, 2024 - link
Thanks for the uncited nonsense Mike, we were all on tenterhooks.Bruzzone - Thursday, June 6, 2024 - link
Thanks BushLin, I also find all the engineering and end use perspectives interesting as a compliment resource specific market observations I triangulate for common perspective and some not so common perspectives from time to time.My full AMD workstation, desktop and mobile what's selling in the last 6 weeks report is now posted at Seeking Alpha.
I posted here in comment string and just look down comments to the pointer and the full report is easily downloadable. There is also a pointer within the downloadable report itself to the same Intel data last eight weeks.
https://seekingalpha.com/article/4697165-computex-...
Mike Bruzzone, Camp Marketing
lmcd - Wednesday, June 12, 2024 - link
if you don't understand how inventory affects pricing then stick to redditballsystemlord - Wednesday, June 5, 2024 - link
In answer to your question, "It's worth the wait to Lunar and Arrow?"In terms of Intel's CPU/GPU performance, I doubt it.
In terms of power efficiency, they might have caught up. We'll have to wait for reviews. Only partially refreshing the screen should lead to a nice performance improvement and/or efficiency improvement of the GPU.
In terms of QoL improvements, it looks like Intel went all out for this new generation. In the following statements, I'm assuming that Intel's able to deliver. Having multiple TB4 ports is useful. Having TB4 with the ability to transfer files is also useful. So is better Wi-Fi. If anything, this might be *the* killer feature of the series. Likewise, VVC, assuming it's not badly licenced, should prove useful. I wonder if VVC is supported by their Quicksync encoder...
Don't misunderstand me, I appreciate what you've said above. But I really don't see this gen failing badly unless AMD/Qualcomm can equal them in terms of useful features.
Bruzzone - Thursday, June 6, 2024 - link
Ballsystemlord,I also think Intel's on it way back to mobile efficiency. While Meteor is ramping, I perceive OEMs from channel data and enterprise IT especially Intel shops on 'applications utility' value, and validation, waiting for Lunar / Arrow and or Strix. Granite Ridge I see facing an AM5 saturation issue and there is sooo much Raphael and Vermeer in the channel to clear R9K price will likely be held up while Raptor/Alder and Raphael/Vermeer nose dive on channel liquidation for capital reclaim to buy new like q4 into first half 2025.
From the channel data AMD and Intel are dumping all over Snapdragon X whose launch is into a deflationary price cycle at least through q1 2025. Lots of downward price and margin pressure.
Me, I am looking for a new (used) laptop, more a desktop replacement than Office low power and AI does not matter to me currently. I was interested in a used Tiger Octa or Cezanne H_ with MXM GPU but waiting a wee bit more because laptop prices including gaming are in a nose dive.
Means I'll be able to move up to new 13th Raptor in overage supply condition or used Alder or Rembrandt H with minimally Ampere. AMD Cezanne and Rembrandt and 13th and 12th pricing just let go and it get's better into q4. See my Seeking Alpha report on supply, trade-in and sales trend pointed to above.
mb
GeoffreyA - Thursday, June 6, 2024 - link
Though my computer is all right, I'd like to upgrade to Cezanne or Renoir, either 5600G or 4600G. (It will likely be the latter because of motherboard woes.) Here, the prices have been stuck for ages. Do you think they'll ever drop?ballsystemlord - Thursday, June 6, 2024 - link
GeoffreyA, I'm not involved with the markets like Mr. Bruzzone, but my recent experience with trying to get a GPU for 4 years in a row says, "Yes, prices will go back down."GeoffreyA - Friday, June 7, 2024 - link
Thanks. It's just puzzling because I don't understand the markets and economic side of things too well.lmcd - Wednesday, June 12, 2024 - link
5600G and 4600G are weird parts because they're dependent on AMD's mobile positioning. The latter (4600G) isn't being manufactured anymore to my knowledge -- Renoir is useless now to AMD because it was supplanted in mobile by the updated Mendocino platform, which likely will never be brought to desktop. I am not sure pricing on the 4600G will ever make sense.5600G is Cezanne, which is still being manufactured for 7x30 series (or was until recently).
However, at this point Cezanne is 7nm and easily binned, but there is no direct 5600G replacement yet as AMD did not launch a 7000 series G product. The 8000G series (just announced) should push 5600G into clearance pricing.
GeoffreyA - Thursday, June 13, 2024 - link
Thanks. Good explanation. I'd go for the 5600G, but my motherboard, B450 Tomahawk, apparently has issues with this very CPU, despite there being BIOS support for quite some time. Online, people haven't had a solution, and MSI says nothing.mode_13h - Thursday, June 6, 2024 - link
Hey, where's the rest of the slide deck? There are definitely some slides I've seen elsewhere that aren't featured in the article. I'm used to this site posting the entire slides at the end.zamroni - Sunday, June 30, 2024 - link
so lunar lake soc die proves that Intel fake 4 is worse than tsmc n6and if the soc / platform controller is included in the compute die, it won't need tsv.
the lunar lake will be much simpler, perform better and might be cheaper